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CS61884 Octal T1/E1/J1 Line Interface Unit
Features
Industry Standard Footprint Octal E1/T1/J1 Short-haul Line Interface Unit Low Power No External Component Changes for 100 /120 /75 Operation Pulse Shapes can be customized by the user Internal AMI, B8ZS, or HDB3 Encoding/Decoding LOS Detection per T1.231, ITU G.775, ETSI 300-233 G.772 Non-Intrusive Monitoring G.703 BITS Clock Recovery Crystal-less Jitter Attenuation Serial/Parallel Microprocessor Control Interfaces Transmitter Short Circuit Current Limiter (<50mA) TX Drivers with Fast High-Z and Power Down JTAG Boundary Scan compliant to IEEE 1149.1 144-Pin LQFP or 160-Pin BGA Package ORDERING INFORMATION CS61884-IQ CS61884-IB 144-pin LQFP 160-pin FBGA
Description
The CS61884 is a full-featured Octal E1/T1/J1 shorthaul LIU that supports both 1.544 Mbps or 2.048 Mbps data transmission. Each channel provides crystal-less jitter attenuation that complies with the most stringent standards. Each channel also provides internal AMI/B8ZS/HDB3 encoding/decoding. To support enhanced system diagnostics, channel zero can be configured for G.772 non-intrusive monitoring of any of the other 7 channels' receive or transmit paths. The CS61884 makes use of ultra low power matched impedance transmitters and receivers to reduce power beyond that achieved by traditional driver designs. By achieving a more precise line match, this technique also provides superior return loss characteristics. Additionally, the internal line matching circuitry reduces the external component count. All transmitters have controls for independent power down and High-Z. Each receiver provides reliable data recovery with over 12 dB of cable attenuation. The receiver also incorporates LOS detection compliant to the most recent specifications. Note: Click on any text in blue to go to cross-references.
LOS RCLK RPOS RNEG
TCLK TPOS TNEG
LOS 0000000000000000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000000000000000 Receiver 0000000000000000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000000000000000 Clock Data 0000000000000000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000000000000000 Recovery Recovery 0000000000000000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000000000000000 Jitter 0000000000000000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000000000000000 Attenuator 0000000000000000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000000000000000 Driver 0000000000000000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000000000000000 Transmit Pulse 0000000000000000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000000000000000 Control Shaper 0000000000000000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000000000000000 0 0000000000000000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000000000000000 1 0000000000000000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000000000000000 Decoder Encoder Remote Loopback Analog Loopback Digital Loopback 7
JTAG Serial Port
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com
000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000000000
JTAG Interface Host Interface
RTIP RRING G.772 Monitor
TTIP TRING
Host Serial/Parallel Port
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2002 (All Rights Reserved)
MAY `02 DS485PP4 1
(c)
CS61884
TABLE OF CONTENTS
1. PINOUT - LQFP ........................................................................................................................................ 7 2. PINOUT - FBGA ........................................................................................................................................ 8 3. PIN DESCRIPTIONS ................................................................................................................................. 9 3.1 Power Supplies .................................................................................................................................. 9 3.2 Control .............................................................................................................................................. 10 3.3 Address Inputs/Loopbacks ............................................................................................................... 14 3.4 Cable Select ..................................................................................................................................... 15 3.5 Status ............................................................................................................................................... 15 3.6 Digital Rx/Tx Data I/O ....................................................................................................................... 16 3.7 Analog RX/TX Data I/O .................................................................................................................... 19 3.8 JTAG Test Interface ......................................................................................................................... 21 3.9 Miscellaneous ................................................................................................................................... 21 4. OPERATION ........................................................................................................................................... 22 5. POWER-UP ............................................................................................................................................. 22 6. MASTER CLOCK .................................................................................................................................... 22 7. G.772 MONITORING ............................................................................................................................... 22 8. BUILDING INTEGRATED TIMING SYSTEMS (BITS) CLOCK MODE .................................................. 23 9. TRANSMITTER ....................................................................................................................................... 24 9.1 Bipolar Mode .................................................................................................................................... 25 9.2 Unipolar Mode .................................................................................................................................. 25 9.3 RZ Mode ........................................................................................................................................... 25 9.4 Transmitter Powerdown / High-Z ...................................................................................................... 25 9.5 Transmit All Ones (TAOS) ................................................................................................................ 25 9.6 Automatic TAOS ............................................................................................................................... 26 9.7 Driver Failure Monitor ....................................................................................................................... 26 9.8 Driver Short Circuit Protection .......................................................................................................... 26 10. RECEIVER ............................................................................................................................................ 26 10.1 Bipolar Output Mode ...................................................................................................................... 26 10.2 Unipolar Output Mode .................................................................................................................... 26 10.3 RZ Output Mode ............................................................................................................................. 27 10.4 Receiver Powerdown/High-Z .......................................................................................................... 27
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/sales.cfm
IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign Trade Law and is to be exported or taken out of the PRC. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
2
DS485PP4
CS61884
10.5 Loss-of-Signal (LOS) .......................................................................................................................27 10.6 Alarm Indication Signal (AIS) ..........................................................................................................28 JITTER ATTENUATOR .........................................................................................................................28 OPERATIONAL SUMMARY ..................................................................................................................29 12.1 Loopbacks .......................................................................................................................................29 12.2 Analog Loopback ............................................................................................................................29 12.3 Digital Loopback ..............................................................................................................................30 12.4 Remote Loopback ...........................................................................................................................30 HOST MODE ..........................................................................................................................................32 13.1 SOFTWARE RESET .......................................................................................................................32 13.2 Serial Port Operation .......................................................................................................................32 13.3 Parallel Port Operation ....................................................................................................................33 13.4 Register Set ....................................................................................................................................34 REGISTER DESCRIPTIONS .................................................................................................................35 14.1 Revision/IDcode Register (00h) ......................................................................................................35 14.2 Analog Loopback Register (01h) .....................................................................................................35 14.3 Remote Loopback Register (02h) ...................................................................................................35 14.4 TAOS Enable Register (03h) ..........................................................................................................35 14.5 LOS Status Register (04h) ..............................................................................................................35 14.6 DFM Status Register (05h) .............................................................................................................35 14.7 LOS Interrupt Enable Register (06h) ...............................................................................................36 14.8 DFM Interrupt Enable Register (07h) ..............................................................................................36 14.9 LOS Interrupt Status Register (08h) ................................................................................................36 14.10 DFM Interrupt Status Register (09h) .............................................................................................36 14.11 Software Reset Register (0Ah) .....................................................................................................36 14.12 Performance Monitor Register (0Bh) ............................................................................................36 14.13 Digital Loopback Reset Register (0Ch) .........................................................................................37 14.14 LOS/AIS Mode Enable Register (0Dh) ..........................................................................................37 14.15 Automatic TAOS Register (0Eh) ...................................................................................................37 14.16 Global Control Register (0Fh) .......................................................................................................38 14.17 Line Length Channel ID Register (10h) .........................................................................................38 14.18 Line Length Data Register (11h) ...................................................................................................39 14.19 Output Disable Register (12h) .......................................................................................................39 14.20 AIS Status Register (13h) .............................................................................................................39 14.21 AIS Interrupt Enable Register (14h) ..............................................................................................39 14.22 AIS Interrupt Status Register (15h) ...............................................................................................40 14.23 AWG Broadcast Register (16h) .....................................................................................................40 14.24 AWG Phase Address Register (17h) ............................................................................................40 14.25 AWG Phase Data Register (18h) ..................................................................................................40 14.26 AWG Enable Register (19h) ..........................................................................................................40 14.27 AWG Overflow Interrupt Enable Register (1Ah) ............................................................................41 14.28 AWG Overflow Interrupt Status Register (1Bh) .............................................................................41 14.29 JA Error Interrupt Enable Register (1Ch) ......................................................................................41 14.30 JA Error Interrupt Status Register (1Dh) .......................................................................................41 14.31 Bits Clock Enable Register (1Eh) ..................................................................................................41 14.32 Reserved Register (1Fh) ...............................................................................................................41 14.33 Status Registers ............................................................................................................................42 14.33.1 Interrupt Enable Registers ...................................................................................................42 14.33.2 Interrupt Status Registers ....................................................................................................42 ARBITRARY WAVEFORM GENERATOR ............................................................................................43 JTAG SUPPORT ....................................................................................................................................45 16.1 TAP Controller .................................................................................................................................45 16.1.1 JTAG Reset ...........................................................................................................................45
11. 12.
13.
14.
15. 16.
DS485PP4
3
CS61884
16.1.2 Test-Logic-Reset ................................................................................................................... 45 16.1.3 Run-Test-Idle ........................................................................................................................ 45 16.1.4 Select-DR-Scan .................................................................................................................... 46 16.1.5 Capture-DR ........................................................................................................................... 46 16.1.6 Shift-DR ................................................................................................................................ 46 16.1.7 Exit1-DR ................................................................................................................................ 46 16.1.8 Pause-DR ............................................................................................................................. 46 16.1.9 Exit2-DR ................................................................................................................................ 46 16.1.10 Update-DR .......................................................................................................................... 46 16.1.11 Select-IR-Scan .................................................................................................................... 47 16.1.12 Capture-IR .......................................................................................................................... 47 16.1.13 Shift-IR ................................................................................................................................ 47 16.1.14 Exit1-IR ............................................................................................................................... 47 16.1.15 Pause-IR ............................................................................................................................. 47 16.1.16 Exit2-IR ............................................................................................................................... 47 16.1.17 Update-IR ........................................................................................................................... 47 16.2 Instruction Register (IR) ................................................................................................................. 47 16.2.1 EXTEST ................................................................................................................................ 47 16.2.2 SAMPLE/PRELOAD ............................................................................................................. 47 16.2.3 IDCODE ................................................................................................................................ 47 16.2.4 BYPASS ............................................................................................................................... 47 16.3 Device ID Register (IDR) ................................................................................................................ 48 BOUNDARY SCAN REGISTER (BSR) ................................................................................................ 48 APPLICATIONS .................................................................................................................................... 51 18.1 Transformer specifications ............................................................................................................. 53 18.2 Crystal Oscillator Specifications ..................................................................................................... 53 18.3 Designing for AT&T 62411 ............................................................................................................. 53 18.4 Line Protection ............................................................................................................................... 53 CHARACTERISTICS AND SPECIFICATIONS ..................................................................................... 54 19.1 Absolute Maximum Ratings ............................................................................................................ 54 19.2 Recommended Operating Conditions ............................................................................................ 54 19.3 Digital Characteristics ..................................................................................................................... 55 19.4 Transmitter Analog Characteristics ................................................................................................ 55 19.5 Receiver Analog Characteristics .................................................................................................... 56 19.6 Jitter Attenuator Characteristics ..................................................................................................... 57 19.7 Master Clock Switching Characteristics ......................................................................................... 59 19.8 Transmit Switching Characteristics ................................................................................................ 59 19.9 Receive Switching Characteristics ................................................................................................. 59 19.10 Switching Characteristics - Serial Port ......................................................................................... 61 19.11 Switching Characteristics - Parallel Port (Multiplexed Mode) ...................................................... 62 19.12 Switching Characteristics- Parallel Port (Non-multiplexed Mode) ............................................... 65 19.13 Switching Characteristics - JTAG ................................................................................................. 68 COMPLIANT RECOMMENDATIONS AND SPECIFICATIONS ........................................................... 69 FBGA PACKAGE DIMENSIONS .......................................................................................................... 70 LQFP PACKAGE DIMENSIONS ..................................................................................................... 71
17. 18.
19.
20. 21. 22.
4
DS485PP4
CS61884
LIST OF FIGURES
Figure 1. CS61884 144-Pin Outs ....................................................................................................... 7 Figure 2. CS61884 160-Ball FBGA Pin Outs .................................................................................... 8 Figure 3. G.703 BITS Clock Mode in NRZ Mode .......................................................................... 23 Figure 4. G.703 BITS Clock Mode in RZ Mode ............................................................................. 23 Figure 5. G.703 BITS Clock Mode in Remote Loopback ............................................................... 23 Figure 6. Pulse Mask at T1/J1 Interface .......................................................................................... 24 Figure 7. Pulse Mask at E1 Interface .............................................................................................. 24 Figure 8. Analog Loopback Block Diagram .................................................................................... 30 Figure 9. Analog Loopback with TAOS Block Diagram ................................................................ 30 Figure 10. Digital Loopback Block Diagram .................................................................................. 31 Figure 11. Digital Loopback with TAOS ........................................................................................ 31 Figure 12. Remote Loopback Block Diagram ................................................................................. 31 Figure 13. Serial Read/Write Format (SPOL = 0) ........................................................................... 33 Figure 14. Arbitrary Waveform UI .................................................................................................. 43 Figure 15. Test Access Port Architecture ........................................................................................ 45 Figure 16. TAP Controller State Diagram ....................................................................................... 46 Figure 17. Internal RX/TX Impedance Matching ............................................................................ 51 Figure 18. Internal TX, External RX Impedance Matching ............................................................ 52 Figure 19. Jitter Transfer Characteristic vs. G.736, TBR 12/13 & AT&T 62411 ........................... 58 Figure 20. Jitter Tolerance Characteristic vs. G.823 & AT&T 62411 ............................................ 58 Figure 21. Recovered Clock and Data Switching Characteristics ................................................... 60 Figure 22. Transmit Clock and Data Switching Characteristics ...................................................... 60 Figure 23. Signal Rise and Fall Characteristics ............................................................................... 60 Figure 24. Serial Port Read Timing Diagram .................................................................................. 61 Figure 25. Serial Port Write Timing Diagram ................................................................................. 61 Figure 26. Parallel Port Timing - Write; Intel Multiplexed Address / Data Bus Mode ................... 63 Figure 27. Parallel Mode Port Timing - Read; Intel Multiplexed Address / Data Bus Mode ........ 63 Figure 28. Parallel Port Timing - Write in Motorola Multiplexed Address / Data Bus .................. 64 Figure 29. Parallel Port Timing - Read in Motorola Multiplexed Address / Data Bus ................... 64 Figure 30. Parallel Port Timing - Write in Intel Non-Multiplexed Address / Data Bus Mode ....... 66 Figure 31. Parallel Port Timing - Read in Intel Non-Multiplexed Address / Data Bus Mode ........ 66 Figure 32. Parallel Port Timing - Write in Motorola Non-Multiplexed Address / Data Bus Mode 67 Figure 33. Parallel Port Timing - Read in Motorola Non-Multiplexed Address / Data Bus Mode . 67 Figure 34. JTAG Switching Characteristics .................................................................................... 68
DS485PP4
5
CS61884
LIST OF TABLES
Table 1. Operation Mode Selection ................................................................................................. 10 Table 2. Mux/Bits Clock Selection .................................................................................................. 11 Table 3. Cable Impedance Selection ................................................................................................ 15 Table 4. G.772 Address Selection .................................................................................................... 22 Table 5. Hardware Mode Line Length Configuration Selection ......................................................25 Table 6. Jitter Attenuator Configurations ......................................................................................... 28 Table 7. Operational Summary ........................................................................................................ 29 Table 8. Host Control Signal Descriptions ...................................................................................... 32 Table 9. Host Mode Register Set ..................................................................................................... 34 Table 10. JTAG Instructions ............................................................................................................ 47 Table 11. Boundary Scan Register ................................................................................................... 48 Table 12. Transformer Specifications .............................................................................................. 53
6
DS485PP4
CS61884
1. PINOUT - LQFP
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
TNEG7/UBS7 RCLK7 RPOS7/RDATA7 RNEG7/BPV7 LOS7 RTIP7 RRING7 TV+7 TTIP7 TRING7 TGND7 RRING6 RTIP6 TGND6 TRING6 TTIP6 TV+6 RTIP5 RRING5 TV+5 TTIP5 TRING5 TGND5 RRING4 RTIP4 TGND4 TRING4 TTIP4 TV+4 CLKE TXOE LOS4 RNEG4/BPV4 RPOS4/RDATA4 RCLK4 TNEG4/UBS4
TPOS7/TDATA7 TCLK7 LOS6 RNEG6/BPV6 RPOS6/RDATA6 RCLK6 TNEG6/UBS6 TPOS6/TDATA6 TCLK6 MCLK MODE A4 A3 A2 A1 A0 VCCIO GNDIO RV0+ RGND0 LOOP0/D0 LOOP1/D1 LOOP2/D2 LOOP3/D3 LOOP4/D4 LOOP5/D5 LOOP6/D6 LOOP7/D7 TCLK1 TPOS1/TDATA1 TNEG1/UBS1 RCLK1 RPOS1/RDATA1 RNEG1/BPV1 LOS1 TCLK0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
26 27 28 29 30 31 32 33 34 35 36
CS6188 4 144-Pin LQFP (Top View)
TPOS4/TDATA4 TCLK4 LOS5 RNEG5/BPV5 RPOS5/RDATA5 RCLK5 TNEG5/UBS5 TPOS5/TDATA5 TCLK5 TDI TDO TCK TMS TRST REF CBLSEL VCCIO GNDIO RV1+ RGND1 INTL/MOT/CODEN CS/JASEL ALE/AS/SCLK/LEN2 RD/RW/LEN1 WR/DS/SDI/LEN0 RDY/ACK/SDO INT TCLK2 TPOS2/TDATA2 TNEG2/UBS2 RCLK2 RPOS2/RDATA2 RNEG2/BPV2 LOS2 TCLK3 TPOS3/TDATA3
DS485PP4
TPOS0/TDATA0 TNEG0/USB0 RCLK0 RPOS0/RDATA0 RNEG0/BPV0 LOS0 MUX/BITSEN0 TV+0 TTIP0 TRING0 TGND0 RTIP0 RRING0 TGND1 TRING1 TTIP1 TV+1 RRING1 RTIP1 TV+2 TTIP2 TRING2 TGND2 RTIP2 RRING2 TGND3 TRING3 TTIP3 TV+3 RRING3 RTIP3 LOS3 RNEG3/RBPV3 RPOS3/RDATA3 RCLK3 TNEG3/UBS3
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
Figure 1. CS61884 144-Pin Outs
7
CS61884
2. PINOUT - FBGA
14 A B C D E F G H J K L M N P
RCLK 4 TCLK 4
13
RPOS 4 TPOS 4
12
RNEG 4 TNEG 4
11
TVCC 4 TVCC 4
10
TRING 4 TTIP 4
9
TGND 4 TGND 4
8
RTIP 4 RRING 4
7
RTIP 7 RRING 7
6
TGND 7 TGND 7
5
TRING 7 TTIP 7
4
TVCC 7 TVCC 7
3
RNEG 7 TNEG 7
2
RPOS 7 TPOS 7
1
RCLK 7 TCLK 7
A B C D E F G H J K L M N P
RCLK 5
RPOS 5
RNEG 5
TVCC 5
TRING 5
TGND 5
RTIP 5
RTIP 6
TGND 6
TRING 6
TVCC 6
RNEG 6
RPOS 6
RCLK 6
TCLK 5
TPOS 5
TNEG 5
TVCC 5
TTIP 5
TGND 5
RRING 5
RRING 6
TGND 6
TTIP 6
TVCC 6
TNEG 6
TPOS 6
TCLK 6
TXOE
CLKE
LOS 5
LOS 4
LOS 7
LOS 6
MODE
MCLK
TCK
TDO
TDI
TMS
A4
A3
A2
A1
VCCIO
CBLSEL
TRST
GNDIO
RV1+
REF
INTL
RGND 1
CS61884 160 FBGA (Bottom View)
GNDIO
A0
LOOP 0 LOOP 2
VCCIO
RGND 0
LOOP 1
RV0+
WR
RD
ALE
CS
LOOP 3 LOS 0 TTIP 2 TGND 2 RRING 2 RRING 1 TGND 1 TTIP 1
LOOP 4 LOS 1
LOOP 5
LOOP 6 LOOP 7
RDY
INT
LOS 2 TNEG 2
LOS 3 TVCC 2
MUX
TCLK 2
TPOS 2
TVCC 1
TNEG 1
TPOS 1
TCLK 1
RCLK 2
RPOS 2
RNEG 2
TVCC 2
TRING 2
TGND 2
RTIP 2
RTIP 1
TGND 1
TRING 1
TVCC 1
RNEG 1
RPOS 1
RCLK 1
TCLK 3 RCLK 3
TPOS 3 RPOS 3
TNEG 3 RNEG 3
TVCC 3 TVCC 3
TTIP 3 TRING 3
TGND 3 TGND 3
RRING 3 RTIP 3
RRING 0 RTIP 0
TGND 0 TGND 0
TTIP 0 TRING 0
TVCC 0 TVCC 0
TNEG 0 RNEG 0
TPOS 0 RPOS 0
TCLK 0 RCLK 0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Figure 2. CS61884 160-Ball FBGA Pin Outs
8
DS485PP4
CS61884
3. PIN DESCRIPTIONS 3.1 Power Supplies
SYMBOL VCCIO GNDIO RV0+ RV1+ RGND0 RGND1 TV+0 TGND0 TV+1 TGND1 TV+2 TGND2 TV+3 TGND3 TV+4 TGND4 TV+5 TGND5 TV+6 TGND6 TV+7 TGND7 LQFP 17 92 18 91 19 90 20 89 44 47 53 50 56 59 65 62 116 119 125 122 128 131 137 134 FBGA G1 G14 G4 G11 H1 H14 H4 H11 N4, P4 N6, P6 L4, M4 L6, M6 L11 M11 L9, M9 N11 P11 N9, P9 A11 B11 A9, B9 C11 D11 C9, D9 C4, D4 C6, D6 A4, B4 A6, B6 TYPE DESCRIPTION Power Supply, Digital Interface: Power supply for digital interface pins; typically 3.3V. Ground, Digital Interface: Power supply ground for the digital interface; typically 0 Volts Power Supply, Core Circuitry: Power supply for all sub-circuits except the transmit driver; typically +3.3 Volts Ground, Core Circuitry: Ground for sub-circuits except the TX driver; typically 0 Volts Power Supply, Transmit Driver 0 Power supply for transmit driver 0; typically +3.3 Volts Ground, Transmit Driver 0 Power supply ground for transmit driver 0; typically 0 Volts Power Supply, Transmit Driver 1 Ground, Transmit Driver 1 Power Supply, Transmit Driver 2 Ground, Transmit Driver 2 Power Supply, Transmit Driver 3 Ground, Transmit Driver 3 Power Supply, Transmit Driver 4 Ground, Transmit Driver 4 Power Supply, Transmit Driver 5 Ground, Transmit Driver 5 Power Supply, Transmit Driver 6 Ground, Transmit Driver 6 Power Supply, Transmit Driver 7 Ground, Transmit Driver 7
DS485PP4
9
CS61884
3.2 Control
SYMBOL LQFP FBGA TYPE DESCRIPTION Master Clock Input This pin is a free running reference clock that should be either 1.544 MHz for T1/J1 or 2.048 MHz for E1 operation. This timing reference is used as follows: - Timing reference for the clock recovery and jitter attenuation circuitry. - RCLK reference during Loss of Signal (LOS) conditions - Transmit clock reference during Transmit all Ones (TAOS) condition - Wait state timing for microprocessor interface - When this pin is held "High", the PLL clock recovery circuit is disabled. In this mode, the CS61884 receivers function as simple data slicers. - When this pin is held "Low", the receiver paths are powered down and the output pins RCLK, RPOS, and RNEG are High-Z. Mode Select This pin is used to select whether the CS61884 operates in Serial host, Parallel host or Hardware mode. Host Mode - The CS61884 is controlled through either a serial or a parallel microprocessor interface (Refer to HOST MODE (See Section 13 on page 32). Hardware Mode - The microprocessor interface is disabled and the device control/status are provided through the pins on the device. MODE 11 E2 I
MCLK
10
E1
I
Table 1. Operation Mode Selection
Pin State LOW HIGH VCCIO/2 OPERATING Mode Hardware Mode Parallel Host Mode Serial Host Mode
NOTE: For serial host mode connect this pin to a resistor divider consisting of two 10K resistors between VCCIO and GNDIO.
10
DS485PP4
CS61884
SYMBOL LQFP FBGA TYPE DESCRIPTION Multiplexed Interface/Bits Clock Select Host Mode -This pin configures the microprocessor interface for multiplexed or non-multiplexed operation. Hardware mode - This pin is used to enable channel 0 as a G.703 BITS Clock recovery channel (Refer to BUILDING INTEGRATED TIMING SYSTEMS (BITS) CLOCK MODE (See Section 8 on page 23). Channel 1 through 7 are not affected by this pin during hardware mode. During host mode the G.703 BITS Clock recovery function is enabled by the Bits Clock Enable Register (1Eh) (See Section 14.31 on page 41).
MUX/BITSEN0
43
K2
I
Table 2. Mux/Bits Clock Selection
Pin State HIGH LOW Parallel Host Mode multiplexed non multiplexed Hardware Mode BITS Clock ON BITS Clock OFF
NOTE: The MUX pin only controls the BITS Clock function in Hardware Mode Interrupt Output This active low output signals the host processor when one of the CS61884's internal status register bits has changed state. When the status register is read, the interrupt is cleared. The various status changes that would force INT active are maskable via internal interrupt enable registers. NOTE: This pin is an open drain output and requires a 10 k pull-up resistor. Data Transfer Acknowledge/Ready/Serial Data Output Intel Parallel Host Mode - During a read or write register access, RDY is asserted "Low" to acknowledge that the device has been accessed. An asserted "High" acknowledges that data has been written or read. Upon completion of the bus cycle, this pin High-Z. Motorola Parallel Host Mode - During a data bus read operation this pin "ACK" is asserted "High" to indicate that data on the bus is valid. An asserted "Low" on this pin during a write operation acknowledges that a data transfer to the addressed register has been accepted. Upon completion of the bus cycle, this pin High-Z. NOTE: Wait state generation via RDY/ACK is disabled in RZ mode (No Clock Recovery). Serial Host Mode - When the microprocessor interface is configured for serial bus operation, "SDO" is used as a serial data output. This pin is forced into a high impedance state during a serial write access. The CLKE pin controls whether SDO is valid on the rising or falling edge of SCLK. Upon completion of the bus cycle, this pin High-Z. Hardware Mode - This pin is not used and should be left open.
INT
82
K13
O
RDY/ACK/SDO
83
K14
O
DS485PP4
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CS61884
SYMBOL LQFP FBGA TYPE DESCRIPTION Data Strobe/ Write Enable/Serial Data/Line Length Input Intel Parallel Host Mode - This pin "WR" functions as a write enable. Motorola Parallel Host Mode - This pin "DS" functions as a data strobe input. Serial Host Mode - This pin "SDI" functions as the serial data input. Hardware Mode - As LEN0, this pin controls the transmit pulse shapes for both E1 and T1/J1 modes. This pin also selects which mode is used E1 or T1/J1 (Refer to Table 5 on page 25). Read/Write/ Read Enable/Line Length Input Intel Parallel Host Mode - This pin "RD" functions as a read enable. Motorola Parallel Host Mode - This pin "R/W" functions as the read/write input signal. Hardware Mode - As LEN1, this pin controls the transmit pulse shapes for both E1 and T1/J1 modes. This pin also selects which mode is used E1 or T1/J1 (Refer to Table 5 on page 25). Address Latch Enable/Serial Clock/Address Strobe/Line Length Input Intel Parallel Host Mode - This pin "ALE" functions as the Address Latch Enable when configured for multiplexed address/data operation. Motorola Parallel Host Mode - This pin "AS" functions as the active "low" address strobe when configured for multiplexed address/data operation. Serial Host Mode - This pin "SCLK" is the serial clock used for data I/O on SDI and SDO. Hardware Mode - As LEN2, this pin controls the transmit pulse shapes for both E1 and T1/J1 modes. This pin also selects which mode is used E1 or T1/J1 (Refer to Table 5 on page 25). Chip Select Input/Jitter Attenuator Select Host Mode - This active low input is used to enable accesses to the microprocessor interface in either serial or parallel mode. Hardware Mode - This pin controls the position of the Jitter Attenuator. Pin State LOW HIGH OPEN Jitter Attenuation Position Transmit Path Receive Path Disabled
WR/DS/SDI/LEN0
84
J14
I
RD/RW/LEN1
85
J13
I
ALE/AS/SCLK/LEN2
86
J12
I
CS/JASEL
87
J11
I
12
DS485PP4
CS61884
SYMBOL LQFP FBGA TYPE DESCRIPTION Motorola/Intel/Coder Mode Select Input Parallel Host Mode - When this pin is "Low" the microprocessor interface is configured for operation with Motorola processors. When this pin is "High" the microprocessor interface is configured for operation with Intel processors. Hardware Mode - When the CS61884 is configured for unipolar operation, this pin, CODEN, configures the line encoding/decoding function. When CODEN is low, B8ZS/HDB3 encoders/decoders are enabled for T1/J1 or E1 operation respectively. When CODEN is high, AMI encoding/decoding is activated. This is done for all eight channels. Transmitter Output Enable Host mode - Operates the same as in hardware mode. Individual drivers can be set to a high impedance state via the Output Disable Register (12h) (See Section 14.19 on page 39). Hardware Mode - When TXOE pin is asserted Low, all the TX drivers are forced into a high impedance state. All other internal circuitry remains active. Clock Edge Select In clock/data recovery mode, setting CLKE "high" will cause RPOS/RNEG to be valid on the falling edge of RCLK and SDO to be valid on the rising edge of SCLK. When CLKE is set "low", RPOS/RNEG is valid on the rising edge of RCLK, and SDO is valid on the falling edge of SCLK. When the part is operated in data recovery mode, the RPOS/RNEG output polarity is active "high" when CLKE is set "high" and active "low" when CLKE is set "low".
INTL/MOT/CODEN
88
H12
I
TXOE
114
E14
I
CLKE
115
E13
I
DS485PP4
13
CS61884
3.3 Address Inputs/Loopbacks
SYMBOL LQFP FBGA TYPE DESCRIPTION Address Selector Input Parallel Host Mode - During non-multiplexed parallel host mode operation, this pin function as the address 4 input for the parallel interface. Hardware Mode - The A4 pin must be tied low at all times. Non-Intrusive Monitoring/Address Selector Inputs Parallel Host Mode - During non-multiplexed parallel host mode operation, these pins function as address A[3:0] inputs for the parallel interface. Hardware Mode - The A[3:0] pins are used for port selection during non-intrusive monitoring. In non-intrusive monitoring mode, receiver 0's input is internally connected to the transmit or receive ports on one of the other 7 channels. The recovered clock and data from the selected port are output on RPOS0/RNEG0 and RCLK0. Additionally, the data from the selected port can be output on TTIP0/TRING0 by activating the remote loopback function for channel 0 (Refer to Performance Monitor Register (0Bh) (See Section 14.12 on page 36). Loopback Mode Selector/Parallel Data Input/Output Parallel Host Mode - In non-multiplexed microprocessor interface mode, these pins function as the bi-directional 8-bit data port. When operating in multiplexed microprocessor interface mode, these pins function as the address and data inputs/outputs. Hardware Mode - No Loopback - The CS61884 is in a normal operating state when LOOP is left open (unconnected) or tied to VCCIO/2. - Local Loopback - When LOOP is tied High, data transmitted on TTIP and TRING is looped back into the analog input of the corresponding channel's receiver and output on RPOS and RNEG. Input Data present on RTIP and RRING is ignored. - Remote Loopback - When LOOP is tied Low the recovered clock and data received on RTIP and RRING is looped back for transmission on TTIP and TRING. Data on TPOS and TNEG is ignored.
A4
12
F4
I
A3 A2 A1 A0
13 14 15 16
F3 F2 F1 G3
I I I I
LOOP0/D0 LOOP1/D1 LOOP2/D2 LOOP3/D3 LOOP4/D4 LOOP5/D5 LOOP6/D6 LOOP7/D7
21 22 23 24 25 26 27 28
G2 H3 H2 J4 J3 J2 J1 K1
I/O I/O I/O I/O I/O I/O I/O I/O
14
DS485PP4
CS61884
3.4 Cable Select
SYMBOL LQFP FBGA TYPE DESCRIPTION Cable Impedance Select Host Mode - The input voltage to this pin does not effect normal operation. Hardware Mode - This pin is used in combination with the LEN control pins (Refer to Table 5, "Hardware Mode Line Length Configuration Selection," on page 25) to set the line impedance for all eight receivers and transmitters. This pin also selects whether or not all eight receivers use an internal or external line matching network (Refer to the Table below for proper settings). CBLSEL 93 G13 I
Table 3. Cable Impedance Selection
E1/T1/J1 T1/J1 T1/J1 T1/J1 E1 E1 E1 CBLSEL No Connect HIGH LOW No Connect HIGH LOW Transmitters 100 Internal 100 Internal 100 Internal 120 Internal 75 Internal 75 Internal Receivers Internal Internal External Inter or Ext Internal External
NOTE: Refer to Figure 17 on page 51 and Figure 18 on page 52 for appropriate external line matching components. All transmitters use internal matching networks.
3.5 Status
SYMBOL LOS0 LOS1 LOS2 LOS3 LOS4 LOS5 LOS6 LOS7 LQFP 42 35 75 68 113 106 3 140 FBGA K4 K3 K12 K11 E11 E12 E3 E4 TYPE O O O O O O O O DESCRIPTION Loss of Signal Output The LOS output pins can be configured to indicate a loss of signal (LOS) state that is compliant to either T1.231, ITU G.775 or ETSI 300 233. These pins are asserted "High" to indicate LOS. The LOS output returns low when an input signal is present for the time period dictated by the associated specification (Refer to Loss-of-Signal (LOS) (See Section 10.5 on page 27)).
DS485PP4
15
CS61884
3.6 Digital Rx/Tx Data I/O
SYMBOL LQFP FBGA TYPE DESCRIPTION Transmit Clock Input Port 0 - When TCLK is active, the TPOS and TNEG pins function as NRZ inputs that are sampled on the falling edge of TCLK. - If MCLK is active, TAOS will be generated when TCLK is held High for 16 MCLK cycles. TCLK0 36 N1 I NOTE: MCLK is used as the timing reference during TAOS and must have the appropriate stability. - If TCLK is held High in the absence of MCLK, the TPOS and TNEG inputs function as RZ inputs. In this mode, the transmit pulse width is set by the pulse-width of the signal input on TPOS and TNEG. To enter this mode, TCLK must be held high for at least 12 S. - If TCLK is held Low, the output drivers enter a low-power, high impedance state. Transmit Positive Pulse/Transmit Data Input Port 0 Transmit Negative Pulse/Unipolar-Bipolar Select Port 0 The function of the TPOS/TDATA and TNEG/UBS inputs are determined by whether Unipolar, Bipolar or RZ input mode has been selected. Bipolar Mode - In this mode, NRZ data on TPOS and TNEG are sampled on the falling edge of TCLK and transmitted onto the line at TTIP and TRING respectively. A "High" input on TPOS results in transmission of a positive pulse; a "High" input on TNEG results in a transmission of a negative pulse. The translation of TPOS/TNEG inputs to TTIP/TRING outputs is as follows: TPOS0/TDATA0 TNEG0/UBS 37 38 N2 N3 I I TPOS 0 1 0 1 TNEG 0 0 1 1 OUTPUT Space Positive Mark Negative Mark Space
Unipolar mode - Unipolar mode is activated by holding TNEG/UBS "High" for more than 16 TCLK cycles, when MCLK is present. The falling edge of TCLK samples a unipolar data steam on TPOS/TDATA. RZ Mode - To activate RZ mode tie TCLK "High" with the absence of MCLK. In this mode, the duty cycle of the TPOS and TNEG inputs determine the pulse width of the output signal on TTIP and TRING.
16
DS485PP4
CS61884
SYMBOL LQFP FBGA TYPE DESCRIPTION Receive Clock Output Port 0 - When MCLK is active, this pin outputs the recovered clock from the signal input on RTIP and RRING. In the event of LOS, the RCLK output transitions from the recovered clock to MCLK. - If MCLK is held "High", the clock recovery circuitry is disabled and the RCLK output is driven by the XOR of RNEG and RPOS. - If MCLK is held "Low", this output is in a high-impedance state. Receive Positive Pulse/ Receive Data Output Port 0 Receive Negative Pulse/Bipolar Violation Output Port 0 The function of the RPOS/RDATA and RNEG/BPV outputs are determined by whether Unipolar, Bipolar, or RZ input mode has been selected. During LOS, the RPOS/RNEG outputs will remain active. NOTE: The RPOS/RNEG outputs can be High-Z by holding MCLK Low. RPOS0/RDATA0 RNEG0/BPV0 40 41 P2 P3 O O Bipolar Output Mode - When configured for Bipolar operation, NRZ Data is recovered from RTIP/RRING and output on RPOS/RNEG. A high signal on RPOS or RNEG correspond to the receipt of a positive or negative pulse on RTIP/RRING respectively. The RPOS/RNEG outputs are valid on the falling or rising edge of RCLK as configured by CLKE. Unipolar Output Mode - When unipolar mode is activated, the recovered data is output on RDATA. The decoder signals bipolar Violations on the RNEG/BPV pin. RZ Output Mode - In this mode, the RPOS/RNEG pins output RZ data recovered by slicing the signal present on RTIP/RRING. A positive pulse on RTIP with respect to RRING generates a logic 1 on RPOS; a positive pulse on RRING with respect to RTIP generates a logic 1 on RNEG. The polarity of the output on RPOS/RNEG is selectable using the CLKE pin. In this mode, external circuitry is used to recover clock from the received signal. Transmit Clock Input Port 1 Transmit Positive Pulse/Transmit Data Input Port 1 Transmit Negative Pulse/Unipolar-Bipolar Select Port 1 Receive Clock Output Port 1 Receive Positive Pulse/ Receive Data Output Port 1 Receive Negative Pulse/Bipolar Violation Output Port 1 Transmit Clock Input Port 2 Transmit Positive Pulse/Transmit Data Input Port 2 Transmit Negative Pulse/Unipolar-Bipolar Select Port 2 17
RCLK0
39
P1
O
TCLK1 TPOS1/TDATA1 TNEG1/UBS1 RCLK1 RPOS1/RDATA1 RNEG1/BPV1 TCLK2 TPOS2/TDATA2 TNEG2/UBS2 DS485PP4
29 30 31 32 33 34 81 80 79
L1 L2 L3 M1 M2 M3 L14 L13 L12
I I I O O O I I I
CS61884
SYMBOL RCLK2 RPOS2/RDATA2 RNEG2/BPV2 TCLK3 TPOS3/TDATA3 TNEG3/UBS3 RCLK3 RPOS3/RDATA3 RNEG3/BPV3 TCLK4 TPOS4/TDATA4 TNEG4/UBS4 RCLK4 RPOS4/RDATA4 RNEG4/BPV4 TCLK5 TPOS5/TDATA5 TNEG5/UBS5 RCLK5 RPOS5/RDATA5 RNEG5/BPV5 TCLK6 TPOS6/TDATA6 TNEG6/UBS6 RCLK6 RPOS6/RDATA6 RNEG6/BPV6 TCLK7 TPOS7/TDATA7 TNEG7/UBS7 LQFP 78 77 76 74 73 72 71 70 69 107 108 109 110 111 112 100 101 102 103 104 105 9 8 7 6 5 4 2 1 144 FBGA M14 M13 M12 N14 N13 N12 P14 P13 P12 B14 B13 B12 A14 A13 A12 D14 D13 D12 C14 C13 C12 D1 D2 D3 C1 C2 C3 B1 B2 B3 TYPE O O O I I I O O O I I I O O O I I I O O O I I I O O O I I I DESCRIPTION Receive Clock Output Port 2 Receive Positive Pulse/ Receive Data Output Port 2 Receive Negative Pulse/Bipolar Violation Output Port 2 Transmit Clock Input Port 3 Transmit Positive Pulse/Transmit Data Input Port 3 Transmit Negative Pulse/Unipolar-Bipolar Select Port 3 Receive Clock Output Port 3 Receive Positive Pulse/ Receive Data Output Port 3 Receive Negative Pulse/Bipolar Violation Output Port 3 Transmit Clock Input Port 4 Transmit Positive Pulse/Transmit Data Input Port 4 Transmit Negative Pulse/Unipolar-Bipolar Select Port 4 Receive Clock Output Port 4 Receive Positive Pulse/ Receive Data Output Port 4 Receive Negative Pulse/Bipolar Violation Output Port 4 Transmit Clock Input Port 5 Transmit Positive Pulse/Transmit Data Input Port 5 Transmit Negative Pulse/Unipolar-Bipolar Select Port 5 Receive Clock Output Port 5 Receive Positive Pulse/ Receive Data Output Port 5 Receive Negative Pulse/Bipolar Violation Output Port 5 Transmit Clock Input Port 6 Transmit Positive Pulse/Transmit Data Input Port 6 Transmit Negative Pulse/Unipolar-Bipolar Select Port 6 Receive Clock Output Port 6 Receive Positive Pulse/ Receive Data Output Port 6 Receive Negative Pulse/Bipolar Violation Output Port 6 Transmit Clock Input Port 7 Transmit Positive Pulse/Transmit Data Input Port 7 Transmit Negative Pulse/Unipolar-Bipolar Select Port 7
18
DS485PP4
CS61884
SYMBOL RCLK7 RPOS7/RDATA7 RNEG7/BPV7 LQFP 143 142 141 FBGA A1 A2 A3 TYPE O O O DESCRIPTION Receive Clock Output Port 7 Receive Positive Pulse/ Receive Data Output Port 7 Receive Negative Pulse/Bipolar Violation Output Port 7
3.7 Analog RX/TX Data I/O
SYMBOL LQFP FBGA TYPE DESCRIPTION Transmit Tip Output Port 0 Transmit Ring Output Port 0 TTIP and TRING pins are the differential outputs of the transmit driver. The driver internally matches impedances for E1 75 , E1 120 and T1/J1 100 lines requiring only a 1:2 transformer. The CBLSEL pin is used to select the appropriate line matching impedance only in "Hardware" mode. In host mode, the appropriate line matching impedance is selected by the Line Length Data Register (11h) (See Section 14.18 on page 39). NOTE: TTIP and TRING are forced to a high impedance state when the TCLK pin is "Low" for over 12S or the TXOE pin is forced "Low". Receive Tip Input Port 0 Receive Ring Input Port 0 RTIP and RRING are the differential line inputs to the receiver. The receiver uses either Internal Line Impedance or External Line Impedance modes to match the line impedances for E1 75, E1 120 or T1/J1 100 modes. Internal Line Impedance Mode - The receiver uses the same external resistors to match the line impedance (Refer to Figure 17 on page 51). External Line Impedance Mode - The receiver uses different external resistors to match the line impedance (Refer to Figure 18 on page 52). - In host mode, the appropriate line impedance is selected by the Line Length Data Register (11h) (See Section 14.18 on page 39). - In hardware mode, the CBLSEL pin in combination with the LEN pins select the appropriate line impedance. (Refer to Table 3 on page 15 for proper line impedance settings). NOTE: Data and clock recovered from the signal input on these pins are output via RCLK, RPOS, and RNEG. TTIP1 TRING1 RTIP1 RRING1 52 51 55 54 L5 M5 M7 L7 O O I I Transmit Tip Output Port 1 Transmit Ring Output Port 1 Receive Tip Input Port 1 Receive Ring Input Port 1
TTIP0 TRING0
45 46
N5 P5
O O
RTIP0 RRING0
48 49
P7 N7
I I
DS485PP4
19
CS61884
SYMBOL TTIP2 TRING2 RTIP2 RRING2 TTIP3 TRING3 RTIP3 RRING3 TTIP4 TRING4 RTIP4 RRING4 TTIP5 TRING5 RTIP5 RRING5 TTIP6 TRING6 RTIP6 RRING6 TTIP7 TRING7 RTIP7 RRING7 LQFP 57 58 60 61 64 63 67 66 117 118 120 121 124 123 127 126 129 130 132 133 136 135 139 138 FBGA L10 M10 M8 L8 N10 P10 P8 N8 B10 A10 A8 B8 D10 C10 C8 D8 D5 C5 C7 D7 B5 A5 A7 B7 TYPE O O I I O O I I O O I I O O I I O O I I O O I I DESCRIPTION Transmit Tip Output Port 2 Transmit Ring Output Port 2 Receive Tip Input Port 2 Receive Ring Input Port 2 Transmit Tip Output Port 3 Transmit Ring Output Port 3 Receive Tip Input Port 3 Receive Ring Input Port 3 Transmit Tip Output Port 4 Transmit Ring Output Port 4 Receive Tip Input Port 4 Receive Ring Input Port 4 Transmit Tip Output Port 5 Transmit Ring Output Port 5 Receive Tip Input Port 5 Receive Ring Input Port 5 Transmit Tip Output Port 6 Transmit Ring Output Port 6 Receive Tip Input Port 6 Receive Ring Input Port 6 Transmit Tip Output Port 7 Transmit Ring Output Port 7 Receive Tip Input Port 7 Receive Ring Input Port 7
20
DS485PP4
CS61884
3.8 JTAG Test Interface
SYMBOL TRST LQFP 95 FBGA G12 TYPE I DESCRIPTION JTAG Reset This active Low input resets the JTAG controller. This input is pulled up internally and may be left as a NC when not used. JTAG Test Mode Select Input This input enables the JTAG serial port when active High. This input is sampled on the rising edge of TCK. This input is pulled up internally and may be left as a NC when not used. JTAG Test Clock Data on TDI is valid on the rising edge of TCK. Data on TDO is valid on the falling edge of TCK. When TCK is stopped high or low, the contents of all JTAG registers remain unchanged. Tie pin low through a 10 K resistor when not used. JTAG Test Data Output JTAG test data is shifted out of the device on this pin. Data is output on the falling edge of TCK. Leave as NC when not used. JTAG Test Data Input JTAG test data is shifted into the device using this pin. The pin is sampled on the rising edge of TCK. TDI is pulled up internally and may be left as a NC when not used.
TMS
96
F11
I
TCK
97
F14
I
TDO
98
F13
O
TDI
99
F12
I
3.9 Miscellaneous
SYMBOL REF LQFP 94 FBGA H13 TYPE I DESCRIPTION Reference Input This pin must be tied to ground through 13.3 K 1% resistor. This pin is used to set the internal current level.
DS485PP4
21
CS61884
4. OPERATION
The CS61884 is a full featured line interface unit for up to eight E1/T1/J1 lines. The device provides an interface to twisted pair or co-axial media. A matched impedance technique is employed that reduces power and eliminates the need for matching resistors. As a result, the device can interface directly to the line through a transformer without the need for matching resistors on the transmit side. The receive side uses the same resistor values for all E1/T1/J1 settings.
7. G.772 MONITORING
The receive path of channel zero of the CS61884 can be used to monitor the receive or transmit paths of any of the other channels. The signal to be monitored is multiplexed to channel zero through the G.772 Multiplexer. The multiplexer and channel zero then form a G.772 compliant digital Protected Monitoring Point (PMP). When the PMP is connected to the channel, the attenuation in the signal path is negligible across the signal band. The signal can be observed using RPOS, RNEG, and RCLK of channel zero or by putting channel zero in remote loopback, the signal can be observed on TTIP and TRING of channel zero. The G.772 monitoring function is available during both host mode and hardware mode operation. In host modes, individual channels are selected for monitoring via the Performance Monitor Register (0Bh) (See Section 14.12 on page 36)). In hardware mode, individual channels are selected through the A3:A0 pins (Refer to Table 4 below for address settings). Table 4. G.772 Address Selection
Address [A3:A0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Channel Selection Monitoring Disabled Receiver Channel # 1 Receiver Channel # 2 Receiver Channel # 3 Receiver Channel # 4 Receiver Channel # 5 Receiver Channel # 6 Receiver Channel # 7 Monitoring Disabled Transmitter Channel # 1 Transmitter Channel # 2 Transmitter Channel # 3 Transmitter Channel # 4 Transmitter Channel # 5 Transmitter Channel # 6 Transmitter Channel # 7
5. POWER-UP
On power-up, the device is held in a static state until the power supply achieves approximately 70% of the power supply voltage. Once the power supply threshold is passed, the analog circuitry is calibrated, the control registers are reset to their default settings, and the various internal state machines are reset. The reset/calibration process completes in about 30 ms.
6. MASTER CLOCK
The CS61884 requires a 2.048 MHz or 1.544 MHz reference clock with a minimum accuracy of 100 ppm. This clock may be supplied from internal system timing or a CMOS crystal oscillator and input to the MCLK pin. The receiver uses MCLK as a reference for clock recovery, jitter attenuation, and the generation of RCLK during LOS. The transmitter uses MCLK as the transmit timing reference during a blue alarm transmit all ones condition. In addition, MCLK provides the reference timing for wait state generation. In systems with a jittered transmit clock, MCLK should not be tied to the transmit clock, a separate crystal oscillator should drive the reference clock input. Any jitter present on the reference clock will not be filtered by the jitter attenuator and can cause the CS61884 to operate incorrectly.
NOTE: In hardware mode the A4 pin must be tied low at all times.
22
DS485PP4
CS61884
8. BUILDING INTEGRATED TIMING SYSTEMS (BITS) CLOCK MODE
This mode is used to enable one or more channels as a stand-alone timing recovery unit used for G.703 Clock Recovery. In hardware mode, BITS Clock mode is selected by pulling the MUX pin "HIGH". This enables only channel zero as a stand-alone timing recovery unit, no other channel can be used as a timing recovery unit.
RCLK RPOS RNEG RRING
In host mode, each channel can be setup as an independent G.703 timing recovery unit, through the Bits Clock Enable Register (1Eh) (See Section 14.31 on page 41), setting the desired bit to "1" enables BITS Clock mode for that channel. The following diagrams show how the BITS clock function operates.
RTIP
CS61884 One Receiver
0 .1 F
R1
RECEIVE LINE
R2
T1 1:2
Figure 3. G.703 BITS Clock Mode in NRZ Mode
RCLK RPOS RNEG
RTIP
CS61884 One Receiver
0 .1 F
R1
RECEIVE LINE
R2
RRING
T1 1:2
Figure 4. G.703 BITS Clock Mode in RZ Mode
RCLK RPOS RNEG
RTIP
CS61884 One Channel
0 .1 F
R1
RECEIVE LINE
R2
RRING REMOTE LOOPBACK TCLK TPOS TNEG TRING TRANMIT LINE
T1 1:2
TTIP
T1 1:2
Figure 5. G.703 BITS Clock Mode in Remote Loopback
DS485PP4
23
CS61884
9. TRANSMITTER
The CS61884 contains eight identical transmitters that each use a low power matched impedance driver to eliminate the need for external load matching resistors, while providing superior return loss. As a result, the TTIP/TRING outputs can be connected directly to the transformer allowing one hardware circuit for 100 (T1/J1), 120 (E1), and 75 (E1) applications. Digital transmit data is input into the CS61884 through the TPOS/TNEG input pins. These pins accept data in one of three formats: unipolar, bipolar, or RZ. In either unipolar or bipolar mode, the CS61884 internally generates a pulse shape compliant to the ANSI T1.102 mask for T1/J1 or the G.703 mask for E1 (Refer to Figure 6 and Figure 7). The pulse shaping applied to the transmit data can be selected in hardware mode or in host mode. In hardware mode, the pulse shape is selected for all channels via the LEN[2:0] pins (Refer to Table 5 on page 25). This sets the pulse shape for all eight transmitters to one of the prestored line lengths. The CBLSEL pin in combination with the LEN[2:0] pins set the line impedance for all eight channels. The CBLSEL pin also selects between E1 120 or E1 75 modes, when the LEN pins are configured for E1 operation mode. In host mode, the pulse shape for each channel can be set independently, during NRZ operation mode, for proper clock recovery and jitter attenuation. In RZ Mode each channel can be set to either T1/J1 or E1, when there is no Mclk present (Refer to RZ Mode (See Section 9.3 on page 25). To select the standard pulse shapes, the channels are selected individually using the Line Length Channel ID Register (10h) (See Section 14.17 on page 38), then the LEN[3:0] bits in the Line Length Data Register (11h) (See Section 14.18 on page 39) are set for the desired line length for that channel. The LEN bits select the line type and im24
pedance for both the receiver and the transmitter of the addressed channel.
NOTE: In host mode the CBLSEL pin is not used.
Normalized Amplitude
1.0
ANSI T1.102, AT&T CB 119 Specifications
0.5
0
Output Pulse Shape
-0.5 0 250 500
TIME (nanoseconds)
750
1000
Figure 6. Pulse Mask at T1/J1 Interface
P erc en t o f no m in al pe ak v olta ge 120 110
2 69 ns
100
90 80
50
10 0 -10 -20
000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 2 44 ns 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 1 94 ns 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 N om ina l P u ls e 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000
2 19 ns 4 88 ns
Figure 7. Pulse Mask at E1 Interface
DS485PP4
CS61884
The CS61884 also allows the user to customize the transmit pulse shapes to compensate for non-standard cables, transformers, or protection circuitry. For further information on the AWG Refer to Arbitrary Waveform Generator (See Section 15 on page 43). For more information on the host mode registers, refer to Register Descriptions (See Section 14 on page 35).
9.3 RZ Mode
In RZ mode, the internal pulse shape circuitry is bypassed and RZ data driven into TPOS/TNEG is transmitted on TTIP/TRING. In this mode, the pulse width of the transmitter output is determined by the width of the RZ signal input to TPOS/TNEG. This mode is entered when MCLK does not exist and TCLK is held "High" for at least 12 sec.
9.1 Bipolar Mode
Bipolar mode provides transparent operation for applications in which the line coding function is performed by an external framing device. In this mode, the falling edge of TCLK samples NRZ data on TPOS/TNEG for transmission on TTIP/TRING.
9.4 Transmitter Powerdown / High-Z
The transmitters can be forced into a high impedance, low power state by holding TCLK of the appropriate channel low for at least 12s or 140 MCLK cycles. In hardware and host mode, the TXOE pin forces all eight transmitters into a high impedance state within 1s. In host mode, each transmitter is individually controllable using the Output Disable Register (12h) (See Section 14.19 on page 39). The TXOE pin can be used in host mode, but does not effect the contents of the Output Enable Register. This feature is useful in applications that require redundancy.
9.2 Unipolar Mode
In unipolar mode, the CS61884 is configured such that transmit data is encoded using B8ZS, HDB3, or AMI line codes. This mode is activated by holding TNEG/UBS "High" for more than 16 TCLK cycles. Transmit data is input to the part via the TPOS/TDATA pin on the falling edge of TCLK. When operating the part in hardware mode, the CODEN pin is used to select between B8ZS/HDB3 or AMI encoding. During host mode operation, the line coding is selected via the Global Control Register (0Fh) (See Section 14.16 on page 38).
NOTE: The encoders/decoders are selected for all eight channels in both hardware and host mode.
9.5 Transmit All Ones (TAOS)
When TAOS is activated, continuous ones are transmitted on TTIP/TRING using MCLK as the transmit timing reference. In this mode, the TPOS and TNEG inputs are ignored. In hardware mode, TAOS is activated by pulling TCLK "High" for more than 16 MCLK cycles.
Table 5. Hardware Mode Line Length Configuration Selection LEN[2:0] 000 001 010 011 100 101 110 111 Transmit Pulse Configuration E1 3.0V / E1 2.37V DS1, Option A (undershoot) DS1, Option A (0 dB) DSX-1: 0-133 ft. (0.6dB) DSX-1: 133-266 ft. (1.2dB) DSX-1: 266-399 ft. (1.8dB) DSX-1: 399-533 ft. (2.4dB) DSX-1: 533-655 ft. (3.0dB) Line Z 120 / 75 100 100 100 100 100 100 100 Operation E1 T1/J1 T1/J1 T1/J1 T1/J1 T1/J1 T1/J1 T1/J1
DS485PP4
25
CS61884
In host mode, TAOS is generated for a particular channel by asserting the associated bit in the TAOS Enable Register (03h) (See Section 14.4 on page 35). Since MCLK is the reference clock, it should be of adequate stability. nal components for 100 (T1/J1), 120 (E1), and 75 (1) operation (Refer to Figure 17 on page 51). This feature enables the use of a one stuffing option for all E1/T1/J1 line impedances. The appropriate E1/T1/J1 line matching is selected via the LEN[2:0] and the CBLSEL pins in hardware mode, or via the Line Length Channel ID Register (10h) (See Section 14.17 on page 38) and bits[3:0] of the Line Length Data Register (11h) (See Section 14.18 on page 39) in host mode. The receivers can also be configured to use different external resistors to match the line impedance for E1 75, E1 120 or T1/J1 100 modes (Refer to Figure 18 on page 52). The CS61884 receiver provides all of the circuitry to recover both data and clock from the data signal input on RTIP and RRING. The matched impedance receiver is capable of recovering signals with 12 dB of attenuation (referenced to 2.37 V or 3.0V nominal) while providing superior return loss. In addition, the timing recovery circuit along with the jitter attenuator provide jitter tolerance that far exceeds jitter specifications (Refer to Figure 20 on page 58). The recovered data and clock is output from the CS61884 on RPOS/RNEG and RCLK. These pins output the data in one of three formats: bipolar, unipolar, or RZ. The CLKE pin is used to configure RPOS/RNEG, so that data is valid on either the rising or falling edge of RCLK.
9.6 Automatic TAOS
While a given channel is in the LOS condition, if the corresponding bit in the Automatic TAOS Register (0Eh) (See Section 14.15 on page 37) is set, the device will drive that channel's TTIP and TRING with the all ones pattern. This function is only available in host mode. Refer to Loss-of-Signal (LOS) (See Section 10.5 on page 27).
9.7 Driver Failure Monitor
In host mode, the Driver Failure Monitor (DFM) function monitors the output of each channel and sets a bit in the DFM Status Register (05h) (See Section 14.6 on page 35) if a secondary short circuit is detected between TTIP and TRING. This generates an interrupt if the respective bit in the DFM Interrupt Enable Register (07h) (See Section 14.8 on page 36) is also set. Any change in the DFM Status Register (05h) (See Section 14.6 on page 35) will result in the corresponding bit in the DFM Interrupt Status Register (09h) (See Section 14.10 on page 36) being set. The interrupt is cleared by reading the DFM Interrupt Status Register (09h) (See Section 14.10 on page 36). This feature works in all modes of operation E1 75 , E1 120 and T1/J1 100 .
10.1 Bipolar Output Mode
Bipolar mode provides a transparent clock/data recovery for applications in which the line decoding is performed by an external framing device. The recovered clock and data are output on RCLK, RNEG/BPV, and RPOS/RDATA.
9.8 Driver Short Circuit Protection
The CS61884 provides driver short circuit protection when current on the secondary exceeds 50 mA RMS during E1/T1/J1 operation modes.
10. RECEIVER
The CS61884 contains eight identical receivers that utilize an internal matched impedance technique that provides for the use of a common set of exter26
10.2 Unipolar Output Mode
In unipolar mode, the CS61884 decodes the recovered data with either B8ZS, HDB3 or AMI line decoding. The decoded data is output on the
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RPOS/RDATA pin. When bipolar violations are detected by the decoder, the RNEG/BPV pin is asserted "High". This pin is driven "high" one RCLK period for every bipolar violation that is not part of the zero substitution rules. Unipolar mode is entered by holding the TNEG pin "High" for more than 16 MCLK cycles. In hardware mode, the B8ZS/HDB3/AMI encoding/Decoding is activated via the CODEN pin. In host mode, the Global Control Register (0Fh) (See Section 14.16 on page 38) is used to select the encoding/decoding for all channels. one "mark" is received. Depending on LOS detection mode, the LOS signal is set when a certain number of consecutive zeros are received. In Clock/Data recovery mode, this forces the recovered clock to be replaced by MCLK at the RCLK output. In addition the RPOS/RNEG outputs are forced "high" for the length of the LOS period except when local and analog loopback are enabled. Upon exiting LOS, the recovered clock replaces MCLK on the RCLK output. In Data recovery mode, RCLK is not replaced by MCLK when LOS is active. The LOS detection modes are summarized below.
NOTE: T1.231, G.775 and ETSI 300 233 are all available in host mode, but in hardware mode only ETSI 300 233 and T1.231 are available.
10.3 RZ Output Mode
In this mode the RTIP and RRING inputs are sliced to data values that are output on RPOS and RNEG. This mode is used in applications that have clock recovery circuitry external to the LIU. To support external clock recovery, the RPOS and RNEG outputs are XORed and output on an edge of RCLK. This mode is entered when MCLK is tied high.
NOTE: The valid RCLK edge of the RPOS/RNEG data is controlled by the CLKE pin.
10.4 Receiver Powerdown/High-Z
All eight receivers are powered down when MCLK is held low. In addition, this will force the RCLK, RPOS, and RNEG outputs into a high impedance state.
ANSI T1.231 (T1/J1 Mode Only) - LOS is detected if the receive signal is less than 200 mV for a period of 176 continuous pulse periods. The channel exits the LOS condition when the pulse density exceeds 12.5% over 176 pulse periods since the receipt of the last pulse. An incoming signal with a pulse amplitude exceeding 250 mV will cause a pulse transition on the RPOS/RDATA or RNEG outputs. ITU G.775 (E1 Mode Only) - LOS is declared when the received signal level is less than 200 mV for 32 consecutive pulse periods (typical). The device exits LOS when the received signal achieves 12.5% ones density with no more than 15 consecutive zeros in a 32 bit sliding window and the signal level exceeds 250 mV. ETSI 300 233 (E1 Host Mode Only) - The LOS indicator becomes active when the receive signal level drops below 200 mV for more than 2048 pulse periods (1 msec). The channel exits the LOS state when the input signal exceeds 250 mV and has transitions for more than 32 pulse periods (16 sec). This LOS detection method can only be selected while in host mode.
10.5 Loss-of-Signal (LOS)
The CS61884 makes use of both analog and digital LOS detection circuitry that is compliant to the latest specifications. During T1/J1 operation ANSI T1.231 is supported and in E1 operation mode, either ITU G.775 or ETSI 300 233 is supported. The LOS condition in E1 mode is changed from ITU G.775 to ETSI 300 233 in the LOS/AIS Mode Enable Register (0Dh) (See Section 14.14 on page 37). The LOS detector increments a counter each time a zero is received, and resets the counter each time a
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During host mode operation, LOS is reported in the LOS Status Monitor Register. Both the LOS pins and the register bits reflect LOS status in host mode operation. The LOS pins and status bits are set high (indicating loss of signal) during reset, power-up, or channel powered-down. trolled by the JASEL pin (Refer to Table 6 for pin configurations). The jitter attenuator's FIFO length and corner frequency, can not be changed in hardware mode. The FIFO length and corner frequency are set to 32 bits and 1.25Hz for the E1 operational modes and to 32 bits and 3.78Hz in the T1/J1 operational modes. Table 6. Jitter Attenuator Configurations
PIN STATE LOW HIGH OPEN JITTER ATTENUATOR POSITON Transmit Path Receive Path Disabled
10.6 Alarm Indication Signal (AIS)
The CS61884 detects all ones alarm condition per the relevant ANSI, ITU, and ETSI specifications. In general, AIS is indicated when the one's density of the receive signal exceeds that dictated by the relevant specification. This feature is only available in host mode (Refer to LOS/AIS Mode Enable Register (0Dh) (See Section 14.14 on page 37)). ANSI T1.231 AIS (T1/J1 Mode) - The AIS condition is declared when less than 9 zeros are received within a sliding window of 8192 bits. This corresponds to a ones density of 99.9% over a period of 5.3 ms. The AIS condition is cleared when nine or more zeros are detected in a sliding window of 8192 bits. ITU G.775 AIS (E1 Mode) - The AIS condition is declared when less than 3 zeros are received within two consecutive 512 bit windows. The AIS condition is cleared when 3 or more zeros are received in two consecutive 512 bit windows. ETSI 300 233 (E1 Mode) - The AIS condition is declared when less than 3 zeros are received in a 512 bit window. The AIS condition is cleared when a 512 bit window is received containing 3 or more zeros.
During host mode operation, the location of the jitter attenuator for all eight channels are set by bits 0 and 1 in the Global Control Register (0Fh) (See Section 14.16 on page 38). The GLOBAL CONTROL REGISTER (0Fh) also configures the jitter attenuator's FIFO length (bit 3) and corner frequency (bit 2). The attenuator consists of a 64-bit FIFO, a narrowband monolithic PLL, and control logic. The jitter attenuator requires no external crystal. Signal jitter is absorbed in the FIFO which is designed to neither overflow nor underflow. If overflow or underflow is imminent, the jitter transfer function is altered to ensure that no bit-errors occur. A configuration option is provided to reduce the jitter attenuator FIFO length from 64 bits to 32 bits in order to reduce propagation delay. The jitter attenuator -3 dB knee frequency depends on the settings of the Jitter Attenuator FIFO length and the Jitter Attenuator Corner Frequency bits 2 and 3, in the Global Control Register (0Fh) (See Section 14.16 on page 38)). Setting the lowest corner frequency guarantees jitter attenuation compliance to European specifications TBR 12/13 and ETSI ETS 300 011 in E1 mode. The jitter attenuator is also compliant with ITU-T G.735, G.742, G.783 and AT&T Pub. 62411 (Refer to Figure 19 on page 58 and Figure 20 on page 58).
11. JITTER ATTENUATOR
The CS61884 internal jitter attenuators can be switched into either the receive or transmit paths. Alternatively, it can be removed from both paths to reduce the propagation delay. During Hardware mode operation, the location of the jitter attenuator for all eight channels are con-
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12. OPERATIONAL SUMMARY
A brief summary of the CS61884 operations in hardware and host mode is provided in Table 7.
Table 7. Operational Summary MCLK Active Active Active Active Active Active Active L L L H H H H H H H H H TCLK Active Active Active L H H H Active H L Active Active Active L L L H H H LOOP Open L H X Open L H X X X Open L H Open L H Open L H Receive Mode RCLK/Data Recovery RCLK/Data Recovery RCLK/Data Recovery RCLK/Data Recovery RCLK/Data Recovery RCLK/Data Recovery RCLK/Data Recovery Power Down Power Down Power Down Data Recovery Data Recovery Data Recovery Data Recovery Data Recovery Data Recovery Data Recovery Data Recovery Data Recovery Transmit Mode Unipolar/Bipolar Unipolar/Bipolar Unipolar/Bipolar Power Down TAOS Unipolar/Bipolar TAOS Unipolar/Bipolar RZ Data Power Down Unipolar/Bipolar RZ Data Unipolar/Bipolar Power Down RZ Data Power Down RZ Data RZ Data RZ Data Loopback Disabled Remote Loopback Analog Loopback Disabled Disabled Remote Loopback Analog Loopback Disabled Disabled Disabled Disabled Remote Loopback Analog Loopback Disabled Remote Loopback Disabled Disabled Remote Loopback Analog Loopback
12.1 Loopbacks
The CS61884 provides three loopback modes for each port. Analog Loopback connects the transmit signal on TTIP and TRING to RTIP and RRING. Digital Loopback Connects the output of the Encoder to the input of the Decoder (through the Jitter Attenuator if enabled). Remote Loopback connects the output of the Clock and Data Recovery block to the input of the Pulse Shaper block. (Refer to detailed descriptions below.) In hardware mode, the LOOP[7:0] pins are used to activate Analog or Remote loopback for each channel. In host mode, the Analog, Digital and Remote Loopback registers are used to enable these functions (Refer to the Analog Loopback Register (01h) (See Section 14.2 on page 35), Remote Loopback Register (02h) (See Section 14.3 on page 35), and Digital Loopback Reset Register (0Ch) (See Section 14.13 on page 37).
12.2 Analog Loopback
In Analog Loopback, the output of the TTIP/TRING driver is internally connected to the input of the RTIP/RRING receiver so that the data on TPOS/TNEG and TCLK appears on the RPOS/RNEG and RCLK outputs. In this mode the RTIP and RRING inputs are ignored. Refer to Figure 8 on page 30. In hardware mode, Analog Loopback is selected by driving LOOP[7:0] high. In host mode, Analog Loopback is selected for a given channel using the appropriate bit in the Analog Loopback Register (01h) (See Section 14.2 on page 35).
NOTE: The simultaneous selection of Analog and Remote loopback modes is not valid. A TAOS request overrides the data on TPOS and TNEG during Analog Loopback. Refer to Figure 9 on page 30.
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Encoder
TPOS TNEG TCLK
Attenuator
Transmit Control & Pulse Shaper
Jitter
TTIP TRING
Decoder
RPOS RNEG RCLK
Attenuator
Jitter
Clock Recovery & Data Recovery
RTIP RRING
Figure 8. Analog Loopback Block Diagram
MCLK TAOS
Encoder
TPOS TNEG TCLK
Attenuator
Transmit Control & Pulse Shaper
Jitter
TTIP TRING (All One's)
Decoder
Jitter
RPOS RNEG RCLK
Attenuator
Clock Recovery & Data Recovery
RTIP RRING
Figure 9. Analog Loopback with TAOS Block Diagram
12.3 Digital Loopback
Digital Loopback causes the TCLK, TPOS, and TNEG (or TDATA) inputs to be looped back through the jitter attenuator (if enabled) to the RCLK, RPOS, and RNEG (or RDATA) outputs. The receive line interface is ignored, but data at TPOS and TNEG (or TDATA) continues to be transmitted to the line interface at TTIP and TRING (Refer to Figure 10 on page 31). Digital Loopback is only available during host mode. It is selected using the appropriate bit in the Digital Loopback Reset Register (0Ch) (See Section 14.13 on page 37).
NOTE: TAOS can also be used during the Digital Loopback operation for the selected channel (Refer to Figure 11 on page 31).
12.4 Remote Loopback
In remote loopback, the RPOS/RNEG and RCLK outputs are internally input to the transmit circuits for output on TTIP/TRING. In this mode the TCLK, TPOS and TNEG inputs are ignored. (Refer to Figure 12 on page 31). In hardware mode, Remote Loopback is selected by driving the LOOP pin for a certain channel low. In host mode, Remote Loopback is selected for a given channel by writing a one to the appropriate bit in the Remote Loopback Register (02h) (See Section 14.3 on page 35).
NOTE: In hardware mode, Remote Loopback overrides TAOS for the selected channel. In host mode, TAOS overrides Remote Loopback.
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Jitter Attenuator
Encoder
TPOS TNEG TCLK
Transmit Control & Pulse Shaper
TTIP TRING
Decoder
RPOS RNEG RCLK
Jitter Attenuator
Clock Recovery & Data Recovery
RTIP RRING
Figure 10. Digital Loopback Block Diagram
MCLK TAOS Jitter Attenuator
Encoder
TPOS TNEG TCLK
Transmit Control & Pulse Shaper
TTIP TRING (All One's)
RPOS RNEG RCLK
Jitter Attenuator
Decoder
Clock Recovery & Data Recovery
RTIP RRING
Figure 11. Digital Loopback with TAOS
Encoder
TPOS TNEG TCLK
Jitter Attenuator
Transmit Control & Pulse Shaper
TTIP TRING
RPOS RNEG RCLK
Jitter Attenuator
Decoder
Clock Recovery & Data Recovery
RTIP RRING
Figure 12. Remote Loopback Block Diagram
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13. HOST MODE
Host mode allows the CS61884 to be configured and monitored using an internal register set. (Refer to Table 1, "Operation Mode Selection," on page 10). The term, "Host mode" applies to both Parallel Host and Serial Host modes. All of the internal registers are available in both Serial and Parallel Host mode; the only difference is in the functions of the interface pins, which are described in Table 8. Serial port operation is compatible with the serial ports of most microcontrollers. Parallel port operation can be configured to be compatible with 8-bit microcontrollers from Motorola or Intel, with both multiplexed or non-multiplexed address/data busses. (Refer to Table 9 on page 34 for host mode registers).
13.2 Serial Port Operation
Serial port host mode operation is selected when the MODE pin is left open or set to VCC/2. In this mode, the CS61884 register set is accessed by setting the chip select (CS) pin low and communicating over the SDI, SDO, and SCLK pins. Timing over the serial port is independent of the transmit and receive system timing. Figure 13 illustrates the format of serial port data transfers. A read or write is initiated by writing an address/command byte (ACB) to SDI. Only the ADR0-ADR4 bits are valid; bits ADR5-ADR6 are do not cares. During a read cycle, the register data addressed by the ACB is output on SDO on the next eight SCLK clock cycles. During a write cycle, the data byte immediately follows the ACB. Data is written to and read from the serial port in LSB first format. When writing to the port, SDI data is sampled by the device on the rising edge of SCLK. The valid clock edge of the data on SDO is controlled by the CLKE pin. When CLKE is low, data on SDO is valid on the falling edge of SCLK. When CLKE is high, data on SDO is valid on the raising edge of SCLK. The SDO pin is Hi-Z when not transmitting. If the host processor has a bidirectional I/O port, SDI and SDO may be tied together.
13.1 SOFTWARE RESET
A software reset can be forced by writing the Software Reset Register (0Ah) (See Section 14.11 on page 36). A software reset initializes all registers to their default settings and initializes all internal state machines.
Table 8. Host Control Signal Descriptions HOST CONTROL SIGNAL DESCRIPTIONS PIN NAME MODE MUX CODEN/MOT/INTL ADDR [4] ADDR[3:0] LOOP[7:0], DATA[7:0] INT SDO/ACK/RDY LEN0/SDI/DS/WR LEN1/R/W/RD LEN2/SCLK/AS/ALE JASEL/CS PIN # 11 43 88 12 13-16 28-21 82 83 84 85 86 87 HARDWARE LOW BITSEN0 CODEN GND ADDR[3:0] LOOP[7:0] Pulled Up NC LEN0 LEN1 LEN2 JASEL SERIAL VDD/2 INT SDO SDI SCLK CS PARALLEL HIGH MUX MOT/INTL ADDR[4] ADDR [3:0] DATA[7:0] INT ACK/RDY DS/WR R/W/RD AS/ALE CS
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As illustrated in Figure 13, the ACB consists of a R/W bit, address field, and two reserved bits. The R/W bit specifies if the current register access is a read (R/W = 1) or a write (R/W = 0) operation. The address field specifies the register address from 0x00 to 0x1f. Non-multiplexed Intel and Motorola modes are shown in Figure 30, Figure 31, Figure 32 and Figure 33. The CS pin initiates the cycle, followed by the DS, RD or WR pin. Data is latched into or out of the part using the rising edge of the DS, WR or RD pin. Raising CS ends the cycle. Multiplexed Intel and Motorola modes are shown in Figure 26, Figure 27, Figure 28 and Figure 29. A read or write is initiated by writing an address byte to D[7:0]. The device latches the address on the falling edge of ALE(AS). During a read cycle, the register data is output during the later portion of the RD or DS pulses. The read cycle is terminated and the bus returns to a high impedance state as RD transitions high in Intel timing or DS transitions high in Motorola timing. During a write cycle, valid write data must be present and held stable during the WR or DS pulses. In Intel mode, the RDY output pin is normally in a high impedance state; it pulses low once to acknowledge that the chip has been selected, and high again to acknowledge that data has been written or read. In Motorola mode, the ACK pin performs a similar function; it drives high to indicate that the address has been received by the part, and goes low again to indicate that data has been written or read.
13.3 Parallel Port Operation
Parallel port host mode operation is selected when the MODE pin is high. In this mode, the CS61884 register set is accessed using an 8-bit, multiplexed bidirectional address/data bus D[7:0]. Timing over the parallel port is independent of the transmit and receive system timing. The device is compatible with both Intel and Motorola bus formats. The Intel bus format is selected when the MOT/INTL pin is high and the Motorola bus format is selected when the MOT/INTL pin is low. In either mode, the interface can have the address and data multiplexed over the same 8-bit bus or on separate busses. This operation is controlled with the MUX pin; MUX = 1 means that the parallel port has its address and data multiplexed over the same bus; MUX = 0 defines a non-multiplexed bus. The timing for the different modes are shown in Figure 26, Figure 27, Figure 28, Figure 29, Figure 30, Figure 31, Figure 32 and Figure 33.
CS
SCLK
SDI
R/W
0
0
0
0
1
0
0
D0
D1
D2
D3
D4
D5
D6
D7
Address/Command Byte
Data Input/Output
SDO CLKE=0
D0
D1
D2
D3
D4
D5
D6
D7
Figure 13. Serial Read/Write Format (SPOL = 0)
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13.4 Register Set
The register set available during host mode operations are presented in Table 9. While the upper
REGISTERS
ADDR NAME Revision/IDCODE Analog Loopback Remote Loopback TAOS Enable LOS Status DFM Status LOS Interrupt Enable DFM Interrupt Enable LOS Interrupt Status DFM Interrupt Status Software Reset Performance Monitor Digital Loopback LOS/AIS Mode Enable Automatic TAOS Global Control Line Length Channel ID Line Length Data Output Disable AIS Status AIS Interrupt Enable AIS Interrupt Status AWG Broadcast AWG Phase Address AWG Phase Data AWG Enable TYPE R R/W R/W R/W R R R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R R/W R/W ALBK 7 RLBK 7 7 6 ALBK 6 5 ALBK 5 4 ALBK 4
three bits of the parallel address are don't cares on the CS61884, they should be set to zero for proper operation.
Table 9. Host Mode Register Set BITS
3 2 1 ALBK 1 0 ALBK 0 IDCODE Refer to Device ID Register (IDR) on page 48 ALBK 3 ALBK 2 RLBK 6 RLBK 5 RLBK 4 RLBK 3 RLBK 2 RLBK 1 RLBK 0
00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h
TAOE 7 TAOE 6 TAOE 5 TAOE 4 TAOE 3 TAOE 2 TAOE 1 TAOE 0 LOSS 7 LOSS 6 LOSS 5 LOSS 4 LOSS 3 LOSS 2 LOSS 1 LOSS 0 DFMS 7 DFMS 6 DFMS 5 DFMS 4 DFMS 3 DFMS 2 DFMS 1 DFMS 0 LOSE 7 LOSE 6 LOSE 5 LOSE 4 LOSE 3 LOSE 2 LOSE 1 LOSE 0 DFME 7 DFME 6 DFME 5 DFME 4 DFME 3 DFME 2 DFME 1 DFME 0 LOSI 7 DFMI 7 RSVD DLBK 7 ATAO 7 AI RSVD RSVD AISS 7 AISE 7 AISI 7 LOSI 6 DFMI 6 RSVD LOSI 5 DFMI 5 RSVD LOSI 4 DFMI 4 RSVD LOSI 3 DFMI 3 A3 LOSI 2 DFMI 2 A2 LOSI 1 DFMI 1 A1 LOSI 0 DFMI 0 A0
SRES 7 SRES 6 SRES 5 SRES 4 SRES 3 SRES 2 SRES 1 SRES 0 DLBK 6 DLBK 5 ATAO 6 Raisen RSVD RSVD AISS 6 AISE 6 AISI 6 ATAO 5 RSVD RSVD RSVD AISS 5 AISE 5 AISI 5 DLBK 4 DLBK 3 DLBK 2 DLBK 1 DLBK 0 ATAO 4 ATAO 3 ATAO 2 ATAO 1 ATAO 0 Coden RSVD IN_EX AISS 4 AISE 4 AISI 4 AISS 3 AISE 3 AISI 3 FIFO RSVD JACF JASEL [1:0] Channel ID LEN[3:0] AISS 2 AISE 2 AISI 2 AISS 1 AISE 1 AISI 1 AISS 0 AISE 0 AISI 0
LAME 7 LAME 6 LAME 5 LAME 4 LAME 3 LAME 2 LAME 1 LAME 0
OENB 7 OENB 6 OENB 5 OENB 4 OENB 3 OENB 2 OENB 1 OENB 0
R/W AWGB 7 AWGB 6 AWGB 5 AWGB 4 AWGB 3 AWGB 2 AWGB 1 AWGB 0 Channel Address [2:0] RSVD Phase Address [4:0] Sample Data[6:0]
19h 1Ah AWG Overflow Interrupt Enable R/W AWGE 7 AWGE 6 AWGE 5 AWGE 4 AWGE 3 AWGE 2 AWGE 1 AWGE 0 1Bh 1Ch 1Dh 1Eh 1Fh
AWG Overflow Interrupt Status RESERVED RESERVED BITS Clock Enable RESERVED R R/W R R/W R/W AWGI 7 AWGI 6 AWGI 5 AWGI 4 AWGI 3 AWGI 2 AWGI 1 AWGI 0 RSVD 6 RSVD 5 RSVD 4 RSVD 3 RSVD 2 RSVD 1 RSVD 0 RSVD 6 RSVD 6 RSVD 5 RSVD 4 RSVD 3 RSVD 2 RSVD 1 RSVD 0 RSVD 6 BITS 7 BITS 6 BITS 5 BITS 4 BITS 3 BITS 2 BITS 1 BITS 0 RSVD 7 RSVD 6 RSVD 5 RSVD 4 RSVD 3 RSVD 2 RSVD 1 RSVD 0
R/W AWGN 7 AWGN 6 AWGN 5 AWGN 4 AWGN 3 AWGN 2 AWGN 1 AWGN 0
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14. REGISTER DESCRIPTIONS 14.1 Revision/IDcode Register (00h)
BIT [7:4] NAME REVI 7-4 Description Bits [7:4] are taken from the least-significant nibble of the Device IDCode, which are 0100. (Refer to Device ID Register (IDR) (See Section 16.3 on page 48). Bits [3:0] are the revision bits from the JTAG IDCODE register, CS61884 Revision A = 0000. These bits are subject to change with the revision of the device (Refer to Device ID Register (IDR) (See Section 16.3 on page 48).
[3:0]
REVI 3-0
14.2 Analog Loopback Register (01h)
BIT [7:0] NAME ALBK 7-0 Description Enables analog loopbacks. A "1" in bit n enables the loopback for channel n. Refer to Analog Loopback (See Section 12.2 on page 29) for a complete explanation. Register bits default to 00h after power-up or reset.
14.3 Remote Loopback Register (02h)
BIT [7:0] Description Enables remote loopbacks. A "1" in bit n enables the loopback for channel n. Refer to RLBK 7-0 Remote Loopback (See Section 12.4 on page 30) for a complete explanation. Register bits default to 00h after power-up or reset. NAME
14.4 TAOS Enable Register (03h)
BIT [7:0] NAME Description TAOE 7-0 A "1" in bit n of this register turns on the TAOS generator in channel n. Register bits default to 00h after power-up or reset.
14.5 LOS Status Register (04h)
BIT [7:0] NAME Description LOSS 7-0 Register bit n is read as "1" when LOS is detected on channel n. Register bits default to 00h after power-up or reset.
14.6 DFM Status Register (05h)
BIT [7:0] NAME Description DFMS 7-0 Driver Failure Monitor. The DFM will set bit n to "1" when it detects a short circuit in channel n. Register bits default to 00h after power-up or reset.
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14.7 LOS Interrupt Enable Register (06h)
BIT [7:0] NAME Description LOSE 7-0 Any change in a LOS Status Register bits will cause the INT pin to go low if corresponding bit in this register is set to "1". Register bits default to 00h after power-up or reset.
14.8 DFM Interrupt Enable Register (07h)
BIT [7:0] Description Enables interrupts for failures detected by the DFM. Any change in a DFM Status Register bit DFME 7-0 will cause an interrupt if the corresponding bit is set to "1" in this register. Register bits default to 00h after power-up or reset. NAME
14.9 LOS Interrupt Status Register (08h)
BIT [7:0] NAME LOSI 7-0 Description Bit n of this register is set to "1" to indicate a status change in bit n of the LOS Status Register. The bits in this register indicate a change in status since the last cleared LOS interrupt. Register bits default to 00h after power-up or reset.
14.10 DFM Interrupt Status Register (09h)
BIT [7:0] NAME DFMI 7-0 Description Bit n of this register is set to "1" to indicate a status change in bit n of the DFM Status Register. The bits in this register indicate a change in status since the last cleared DFM interrupt. Register bits default to 00h after power-up or reset.
14.11 Software Reset Register (0Ah)
BIT [7:0] NAME Description SRES 7-0 Writing to this register initializes all registers to their default settings. Register bits default to 00h after power-up or reset.
14.12 Performance Monitor Register (0Bh)
BIT [7:4] NAME RSVD 7-4 Description RESERVED (These bits must be set to 0.)
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(Continued)
BIT NAME Description The G.772 Monitor is directed to a given channel based on the state of the four least significant bits of this register. Register bits default to 00h after power-up or reset. The following table shows the settings needed to select a specific channel's receiver or transmitter to perform G.772 monitoring. A[3:0] Channel Selection 0000 Monitoring Disabled 0001 RX Channel #1 0010 RX Channel #2 0011 RX Channel #3 0100 RX Channel #4 0101 RX Channel #5 0110 RX Channel #6 0111 RX Channel #7 1000 Monitoring Disabled 1001 TX Channel #1 1010 TX Channel #2 1011 TX Channel #3 1100 TX Channel #4 1101 TX Channel #5 1110 TX Channel #6 1111 TX Channel #7
[3:0]
A[3:0]
14.13 Digital Loopback Reset Register (0Ch)
BIT [7:0] NAME Description DLBK 7-0 Setting register bit n to "1" enables the digital loopback for channel n. Refer to Digital Loopback (See Section 12.3 on page 30) for a complete explanation. Register bits default to 00h after power-up or reset.
14.14 LOS/AIS Mode Enable Register (0Dh)
BIT [7:0] NAME Description LAME 7-0 T1/J1 MODE - These bits are "Do Not Care", T1.231 Compliant LOS/AIS already used. E1 Mode - Setting bit n to "1" enables ETSI 300 233 compliant LOS/AIS for channel n; setting bit n to "0" enables ITU G.775 compliant LOS/AIS for channel n. Register bits default to 00h after power-up or reset.
14.15 Automatic TAOS Register (0Eh)
BIT [7:0] NAME Description ATAO 7-0 Setting bit n to "1" enables automatic TAOS generation on channel n when LOS is detected. Register bits default to 00h after power-up or reset.
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14.16 Global Control Register (0Fh)
BIT Description This register is the global control for the AWG Auto-Increment, Automatic AIS insertion, encoding/decoding and the jitter attenuators location, FIFO length and corner frequency for all eight channels. Register bits default to 00h after power-up or reset. The AWG Auto-Increment bit indicates whether to auto-increment the AWG Phase Address AWG Auto- Register (17h) (See Section 14.24 on page 40) after each access. Thus, when this bit is set, Increment the phase samples address portion of the address register increments after each read or write access. This bit must be set before any bit in the AWG Enable register is set, if this function is required. On LOS, this bit controls the automatic AIS insertion into all eight receiver paths. RAISEN 0 = Disabled 1 = Enabled RSVD RESERVED (This bit must be set to 0.) Line encoding/decoding Selection 0 = B8ZS/HDB3 (T1/J1/E1 respectively) CODEN 1 = AMI Jitter Attenuator FIFO length Selection FIFO 0 = 32 bits LENGTH 1 = 64 bits Jitter Attenuator Corner Frequency Selection E1 T1/J1 JACF 0 = 1.25Hz 3.78Hz 1 = 2.50Hz 7.56Hz These bits select the position of the Jitter Attenuator. JASEL 1 JASEL 0 0 0 0 1 1 0 1 1 POSITION Disabled Transmit Path Disabled Receive Path NAME
[7]
[6] [5] [4]
[3]
[2]
[1:0]
JASEL [1:0]
14.17 Line Length Channel ID Register (10h)
BIT [7:3] NAME RSVD 7-3 Description RESERVED (These bits must be set to 0.) The value written to these bits specify the LIU channel for which the Pulse Shape Configuration Data (register 11h) applies. For example, writing a value of a binary 000 to the 3-LSBs will select channel 0. The pulse shape configuration data for the channel specified in this register are written or read through the Line Length Data Register (11h). Register bits default to 00h after power-up or reset.
[2:0]
LLID 2-0
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14.18 Line Length Data Register (11h)
BIT Description The value written to the 4-LSBs of this register specifies whether the device is operating in either T1/J1 or E1 modes and the associated pulse shape as shown below is being transmitted. Register bits default to 00h after power-up or reset. RSVD RESERVED (These bits must be set to 0.) This bit specifies the use of internal (Int_ExtB = 1) or external (Int_ExtB = 0) receiver line INT_EXTB matching. The line impedance for both the receiver and transmitter are chosen through the LEN [3:0] bits in this register. These bits setup the line impedance for both the receiver and the transmitter path and the LEN[3:0] desired pulse shape for a specific channel. The channel is selected with the Line Length Channel ID register (0x10). The following table shows the available transmitter pulse shapes. LEN [3:0] Operation Line Length Selection Phase Samples Mode per UI 0000 E1 120 3.0V 12 0001 T1/J1 100 DS1, Option A (undershoot) 14 0010 T1/J1 100 DS1, Option A (0dB) 14 0011 T1/J1 100 0 - 133Ft (0.6dB) 13 0100 T1/J1 100 133 - 266Ft (1.2dB) 13 0101 T1/J1 100 266 - 399Ft (1.2dB) 13 0110 T1/J1 100 399 - 533Ft (2.4dB) 13 0111 T1/J1 100 533 - 655Ft (3.0dB) 13 1000 E1 75 2.37V 12 NAME
[7:5] [4]
[3:0]
14.19 Output Disable Register (12h)
BIT [7:0] NAME Description OENB 7-0 Setting bit n of this register to "1" High-Z the TX output driver on channel n of the device. Register bits default to 00h after power-up or reset.
14.20 AIS Status Register (13h)
BIT [7:0] NAME AISS 7-0 Description A "1" in bit position n indicates that the receiver has detected an AIS condition on channel n, which generates an interrupt on the INT pin. Register bits default to 00h after power-up or reset.
14.21 AIS Interrupt Enable Register (14h)
BIT [7:0] NAME AISE 7-0 Description This register enables changes in the AIS Status register to be reflected in the AIS Interrupt Status register, thus causing an interrupt on the INT pin. Register bits default to 00h after power-up or reset.
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14.22 AIS Interrupt Status Register (15h)
BIT [7:0] NAME AISI 7-0 Description Bit n is set to "1" to indicate a change of status of bit n in the AIS Status Register. The bits in this register indicate which channel changed in status since the last cleared AIS interrupt. Register bits default to 00h after power-up or reset.
14.23 AWG Broadcast Register (16h)
BIT [7:0] Description Setting bit n to "1" causes the phase data in the AWG Phase Data Register to be written to AWGB 7-0 the corresponding channel or channels simultaneously. (Refer to Arbitrary Waveform Generator (See Section 15 on page 43). Register bits default to 00h after power-up or reset. NAME
14.24 AWG Phase Address Register (17h)
BIT [7:5] [4:0] NAME AWGA PA[4:0] Description These bits specify the target channel 0-7. (Refer to Arbitrary Waveform Generator (See Section 15 on page 43). Register bits default to 00h after power-up or reset. These bits specify 1 of 24 (E1) or 26/28 (T1/J1) phase sample address locations of the AWG, that the phase data in the AWG Phase Data Register is written to or read from. The other locations in each channel's phase sample addresses are not used, and should not be accessed. Register bits default to 00h after power-up or reset.
14.25 AWG Phase Data Register (18h)
BIT [7] Description RESERVED (This bit must be set to 0.) These bits are used for the pulse shape data that will be written to the AWG phase location specified by the AWG Phase Address Register. The value written to or read from this register will be written to or read from the AWG phase sample location specified by the AWG Phase AWGD [6:0] Address register. A software reset through the Software Reset Register does not effect the contents of this register. The data in each phase is a 7-bit 2's complement number (the maximum positive value is 3Fh and the maximum negative value is 40h). (Refer to Arbitrary Waveform Generator (See Section 15 on page 43). Register bits default to 00h after power-up. NAME RSVD
[6:0]
14.26 AWG Enable Register (19h)
BIT Description The AWG enable register is used for selecting the source of the customized transmission pulse-shape. Setting bit n to "1" in this register selects the AWG as the source of the output AWGN 7-0 pulse shape for channel n. When bit n is set to "0" the pre-programmed pulse shape in the ROM is selected for transmission on channel n. (Refer to Arbitrary Waveform Generator (See Section 15 on page 43). Register bits default to 00h after power-up or reset. NAME
[7:0]
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14.27 AWG Overflow Interrupt Enable Register (1Ah)
BIT [7:0] Description This register enables changes in the overflow status to be reflected in the AWG Interrupt StaAWGE 7-0 tus register, thus causing as interrupt on the INT pin. Interrupts are maskable on a per-channel basis. Register bits default to 00h after power-up or reset. NAME
14.28 AWG Overflow Interrupt Status Register (1Bh)
BIT [7:0] Description The bits in this register indicate a change in status since the last AWG overflow interrupt. An AWGI 7-0 AWG overflow occurs when invalid phase data are entered, such that a sample-by-sample addition of UI0 and UI1 results in values that exceed the arithmetic range of the 7-bit representation. Reading this register clears the interrupt, which deactivates the INT pin. Register bits default to 00h after power-up or reset. NAME
14.29 Reserved Register (1Ch)
BIT [7:0] NAME RSVD 7-0 Description RESERVED (These bits must be set to zero.)
14.30 Reserved Register (1Dh)
BIT [7:0] NAME RSVD 7-0 Description RESERVED (These bits must be set to zero.)
14.31 Bits Clock Enable Register (1Eh)
BIT [7:0] NAME BITS 7-0 Description Setting a "1" to bit n in this register changes channel n to a stand-alone timing recovery unit used for G.703 clock recovery. (Refer to BUILDING INTEGRATED TIMING SYSTEMS (BITS) CLOCK MODE (See Section 8 on page 23) for a better description of the G.703 clock recovery function). Register bits default to 00h after power-up or reset.
14.32 Reserved Register (1Fh)
BIT [7:0] NAME RSVD 7-0 Description RESERVED (These bits must be set to zero.)
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14.33 Status Registers
The following Status registers are read-only: LOS Status Register (04h) (See Section 14.5 on page 35), DFM Status Register (05h) (See Section 14.6 on page 35) and AIS Status Register (13h) (See Section 14.20 on page 39). The CS61884 generates an interrupt on the INT pin any time an unmasked status register bit changes. on the INT pin. Interrupts are maskable on a per channel basis. When an Interrupt Enable register bit is 0, the corresponding Status register bit is disabled from causing an interrupt on the INT pin.
NOTE: Disabling an interrupt has no effect on the status reflected in the associated status register.
14.33.2 Interrupt Status Registers
The following interrupt status registers: LOS Interrupt Status Register (08h) (See Section 14.9 on page 36), DFM Interrupt Status Register (09h) (See Section 14.10 on page 36), AIS Interrupt Status Register (15h) (See Section 14.22 on page 40) and AWG Overflow Interrupt Status Register (1Bh) (See Section 14.28 on page 41), indicate a change in status of the corresponding status registers in host mode. Reading these registers clears the interrupt, which deactivates the INT pin.
14.33.1 Interrupt Enable Registers
The Interrupt Enable registers: LOS Interrupt Enable Register (06h) (See Section 14.7 on page 36), DFM Interrupt Enable Register (07h) (See Section 14.8 on page 36), AIS Interrupt Enable Register (14h) (See Section 14.21 on page 39) and AWG Overflow Interrupt Enable Register (1Ah) (See Section 14.27 on page 41), enable changes in status register state to cause an interrupt
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15. ARBITRARY WAVEFORM GENERATOR
Using the Arbitrary Waveform Generator (AWG) allows the user to customize the transmit pulse shapes to compensate for nonstandard cables, transformers, protection circuitry, or to reduce power consumption by reducing the output pulse amplitude. A channel is configured for a custom pulse shape by storing data representing the pulse shape into the 24/26/28 phase sample locations and then enabling the AWG for that channel. Each channel has a separate AWG, so all eight channels can have a different customized pulse shape. The microprocessor interface, is used to read from or write to the AWG, while the device is in host mode. In the AWG RAM, the pulse shape is divided into two unit intervals (UI). For E1 mode, there are 12 sample phases in each UI, while in T1/J1 mode, the number of sample phases per UI are either 13 or 14. The first UI is for the main part of the pulse and the second UI is for the "tail" of the pulse (Refer to Figure 14). A complete pulse-shape is represented by 24 phase samples in E1 mode or 26/28 phase samples in T1/J1 mode. In E1 mode, data written in the first UI represents a valid pulse shape, while data in the second UI is ignored and should be set to zero. The mode of operation is selected using the Line Length Channel ID Register (10h) (See Section 14.17 on page 38) and the Line Length Data Register (11h) (See Section 14.18 on page 39). A phase sample, or cell, is accessed by first loading the channel address and the phase sample address into the AWG Phase Address Register (17h) (See Section 14.24 on page 40), and then reading or writing the AWG Phase Data Register (18h) (See Section 14.25 on page 40). The upper locations in each channel's address space are not used; reading and writing to these registers produces undefined results. The data in each phase sample is a 7-bit two's complement number with a maximum positive value of 0x3f, and a maximum negative value of 0x40. The terms "positive" and "negative" are defined for a positive going pulse only. The pulse generation circuitry automatically inverts the pulse for negative going pulses. The data stored in the lowest phase address corresponds to the first phase sample that will be transmitted in time. When the mode of operation calls for only 24/26 phase samples if the phase samples that are not used (25 through 28) are written to, they are ignored and don't effect the shape of the customized pulse shape. The following procedure describes how to enable and write data into the AWG to produce customized pulse shapes to be transmitted for a specific
U1 U2
E1 AWG Example U1 U2
DSX-1 (54% duty cycle) AWG Example U1 U2
DSX-1 (50% duty cycle) AWG Example
Figure 14. Arbitrary Waveform UI
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channel or channels. To enable the AWG function for a specific channel or channels the corresponding bit(s) in the AWG Enable Register (19h) (See Section 14.26 on page 40) must be set to "1". When the corresponding bit(s) in the AWG Enable Register are set to "0" pre-programmed pulse shapes are selected for transmission. In order to access and write data for a customized pulse shape to a specific channel or channels, the following steps are required. First the desired channel and phase sample addresses must be written to the AWG Phase Data Register (18h) (See Section 14.25 on page 40). Once the channel and phase sample address have been selected, the actual phase sample data may be entered into the AWG Phase Data Register at the selected phase sample address selected by the lower five bits of the AWG Phase Address Register (17h) (See Section 14.24 on page 40)). To change the phase sample address of the selected channel the user may use either of the following steps. First, the user can re-write the phase sample address to the AWG Phase Address Register or set the Auto-Increment bit (Bit 7) in the Global Control Register (0Fh) (See Section 14.16 on page 38)) to "1". When this bit is set to "1" only the first phase sample address (00000 binary) needs to be written to the AWG Phase Address Register (17h) (See Section 14.24 on page 40), and each subsequent access (read or write) to the AWG Phase Data Register (18h) (See Section 14.25 on page 40) will automatically increment the phase sample address. The channel address, however, remains unaffected by the Auto-Increment mode. Since the number of phase samples forming the customized pulse shape varies with the mode of operation (E1/T1/J1), the AWG Phase Address Register (17h) (See Section 14.24 on page 40) needs to be re-written in order to re-start the phase sample address sequence from zero. The AWG Broadcast function allows the same data to be written to different channels simultaneously. This is done with the use of the AWG Broadcast Register (16h) (See Section 14.23 on page 40)), each bit in the AWG Broadcast Register corresponds to a different channel (bit 0 is channel 0, and bit 3 is channel 3 & etc.). To write the same pulse shaping data to multiple channels, simple set the corresponding bit to "1" in the AWG Broadcast Register (16h) (See Section 14.23 on page 40). This function only requires that one of the eight channel addresses be written to the AWG Phase Address Register (17h) (See Section 14.24 on page 40). During an AWG read sequence, the bits in the AWG Broadcast Register are ignored. During an AWG write sequence, the selected channel or channels are specified by both the channel address specified by the upper bits of the AWG Phase Address Register (17h) (See Section 14.24 on page 40) and the selected channel or channels in the AWG Broadcast Register (16h) (See Section 14.23 on page 40). During a multiple channel write the first channel that is written to, is the channel that was address by the AWG Phase Address Register. This channel's bit in the AWG Broadcast Register can be set to either "1" or "0". For a more descriptive explanation of how to use the AWG refer to the "How To Use The CS61880/CS61884 Arbitrary Waveform Generator" application note AN204.
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16. JTAG SUPPORT
The CS61884 supports the IEEE Boundary Scan Specification as described in the IEEE 1149.1 standards. A Test Access Port (TAP) is provided that consists of the TAP controller, the instruction register (IR), by-pass register (BPR), device ID register (IDR), the boundary scan register (BSR), and the 5 standard pins (TRST, TCK, TMS, TDI, and TDO). A block diagram of the test access port is shown in Figure 15. The test clock input (TCK) is used to sample input data on TDI, and shift output data through TDO. The TMS input is used to step the TAP controller through its various states. The instruction register is used to select test execution or register access. The by-pass register provides a direct connection between the TDI input and the TDO output. The device identification register contains an 32-bit device identifier. The Boundary Scan Register is used to support testing of IC inter-connectivity. Using the Boundary Scan Register, the digital input pins can be sampled and shifted out on TDO. In addition, this register can also be used to drive digital output pins to a user defined state.
16.1 TAP Controller
The TAP Controller is a 16 state synchronous state machine clocked by the rising edge of TCK. The TMS input governs state transitions as shown in Figure 16. The value shown next to each state transition in the diagram is the value that must be on TMS when it is sampled by the rising edge of TCK.
16.1.1 JTAG Reset
TRST resets all JTAG circuitry.
16.1.2 Test-Logic-Reset
The test-logic-reset state is used to disable the test logic when the part is in normal mode of operation. This state is entered by asynchronously asserting TRST or forcing TMS High for 5 TCK periods.
16.1.3 Run-Test-Idle
The run-test-idle state is used to run tests.
Digital output pins Digital input pins parallel latched output Boundary Scan Data Register TDI Device ID Data Register MUX Bypass Data Register TCK Instruction (shift) Register parallel latched output TAP Controller TDO JTAG BLOCK
TMS
Figure 15. Test Access Port Architecture
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1
Test-Logic-Reset 0 1 1 1
0
Run-Test/Idle
Select-DR-Scan 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0
Select- IR-Scan 0 1 Capture- IR 0 0 Shift- IR 1
0 1
1
Exit1- IR 0 0 0 Pause- IR 1 Exit2- IR 1 Update- I R 1 0
0
Figure 16. TAP Controller State Diagram
16.1.4 Select-DR-Scan
This is a temporary controller state.
16.1.8 Pause-DR
The pause state allows the test controller to temporarily halt the shifting of data through the current test data register.
16.1.5 Capture-DR
In this state, the Boundary Scan Register captures input pin data if the current instruction is EXTEST or SAMPLE/PRELOAD.
16.1.9 Exit2-DR
This is a temporary state. The test data register selected by the current instruction retains its previous value.
16.1.6 Shift-DR
In this controller state, the active test data register connected between TDI and TDO, as determined by the current instruction, shifts data out on TDO on each rising edge of TCK.
16.1.10 Update-DR
The Boundary Scan Register is provided with a latched parallel output to prevent changes while data is shifted in response to the EXTEST and SAMPLE/PRELOAD instructions. When the TAP controller is in this state and the Boundary Scan Register is selected, data is latched into the parallel output of this register from the shift-register path on the falling edge of TCK. The data held at the latched parallel output changes only in this state.
16.1.7 Exit1-DR
This is a temporary state. The test data register selected by the current instruction retains its previous value.
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16.1.11 Select-IR-Scan
This is a temporary controller state. The test data register selected by the current instruction retains its previous state. by the current instruction retain their previous value.
16.2 Instruction Register (IR)
The 3-bit Instruction register selects the test to be performed and/or the data register to be accessed. The valid instructions are shifted in LSB first and are listed in Table 10: Table 10. JTAG Instructions
IR CODE 000 100 110 111 INSTRUCTION EXTEST SAMPLE/PRELOAD IDCODE BYPASS
16.1.12 Capture-IR
In this controller state, the instruction register is loaded with a fixed value of "01" on the rising edge of TCK. This supports fault-isolation of the boardlevel serial test data path.
16.1.13 Shift-IR
In this state, the shift register contained in the instruction register is connected between TDI and TDO and shifts data one stage towards its serial output on each rising edge of TCK.
16.2.1 EXTEST
The EXTEST instruction allows testing of off-chip circuitry and board-level interconnect. EXTEST connects the BSR to the TDI and TDO pins.
16.1.14 Exit1-IR
This is a temporary state. The test data register selected by the current instruction retains its previous value.
16.2.2 SAMPLE/PRELOAD
The SAMPLE/PRELOAD instruction samples all device inputs and outputs. This instruction places the BSR between the TDI and TDO pins. The BSR is loaded with samples of the I/O pins by the Capture-DR state.
16.1.15 Pause-IR
The pause state allows the test controller to temporarily halt the shifting of data through the instruction register.
16.1.16 Exit2-IR
This is a temporary state. The test data register selected by the current instruction retains its previous value.
16.2.3 IDCODE
The IDCODE instruction connects the device identification register to the TDO pin. The device identification code can then be shifted out TDO using the Shift-DR state.
16.1.17 Update-IR
The instruction shifted into the instruction register is latched into the parallel output from the shift-register path on the falling edge of TCK. When the new instruction has been latched, it becomes the current instruction. The test data registers selected
16.2.4 BYPASS
The BYPASS instruction connects a one TCK delay register between TDI and TDO. The instruction is used to bypass the device.
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16.3 Device ID Register (IDR)
Revision section: 0h = Rev A, 1h = Rev B and so on. The device Identification Code [27 - 12] is derived from the last three digits of the part number (884). The LSB is a constant 1, as defined by IEEE 1149.1. CS61884 IDCODE REGISTER(IDR)
REVISION 0h 0 0 0 0 0 0 0h 0 0 1 0 DEVICE IDCODE REGISTER 8h 0 0 1 0 8h 0 0 0 1 4h 0 0 0 MANUFACTURER CODE 0h Oh 9h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0011001001
17. BOUNDARY SCAN REGISTER (BSR)
The BSR is a shift register that provides access to the digital I/O pins. The BSR is used to read and write the device pins to verify interchip connectivity. Each pin has a corresponding scan cell in the register. The pin to scan cell mapping is given in the BSR description shown in Table 11.
NOTE: Data is shifted LSB first into the BSR register. Table 11. Boundary Scan Register BSR Bit
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
Pin Name
LOS7 RNEG7 RPOS7 RCLK7 TNEG7 TPOS7 TCLK7 LOS6 RNEG6 RPOS6 RCLK6 TNEG6 TPOS6 TCLK6 MCLK MODE MODE ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 LOOP0/D0 LOOP0/D0 LOOP0/D0 LOOP1/D1
Cell Type
O O O O Note 2 I I I O O O O Note 2 I I I I I I I I I I I I I O I
Bit Symbol
LOS7 RNEG7 RPOS7 RCLK7 HIZ7_B TNEG7 TPOS7 TCLK7 LOS6_B RNEG6 RPOS6 RCLK6 HIZ6_B TNEG6 TPOS6 TCLK6 MCLK MODE_TRI MODE_IN ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 LPT0 LPI0 LPO0 LPT1
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Table 11. Boundary Scan Register (Continued) BSR Bit
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
Pin Name
LOOP1/D1 LOOP1/D1 LOOP2/D2 LOOP2/D2 LOOP2/D2 LOOP3/D3 LOOP3/D3 LOOP3/D3 LOOP4/D4 LOOP4/D4 LOOP4/D4 LOOP5/D5 LOOP5/D5 LOOP5/D5 LOOP6/D6 LOOP6/D6 LOOP6/D6 LOOP7/D7 LOOP7/D7 LOOP7/D7 TCLK1 TPOS1 TNEG1 RCLK1 RPOS1 RNEG1 LOS1 TCLK0 TPOS0 TNEG0 RCLK0 RPOS0 RNEG0 LOS0 MUX LOS3 RNEG3 RPOS3 RCLK3 TNEG3 TPOS3
Cell Type
I O I I O I I O I I O I I O I I O I I O Note 1 I I I O O O Note 2 O I I I O O O Note 2 O I O O O O Note 2 I I
Bit Symbol
LPI1 LPO1 LPT2 LPI2 LPO2 LPT3 LPI3 LPO3 LPT4 LPI4 LPO4 LPT5 LPI5 LPO5 LPT6 LPI6 LPO6 LPT7 LPI7 LPO7 LPOEN TCLK1 TPOS1 TNEG1 RCLK1 RPOS1 RNEG1 HIZ1_B LOS1 TCLK0 TPOS0 TNEG0 RCLK0 RPOS0 RNEG0 HIZ0_B LOS0 MUX LOS3 RNEG3 RPOS3 RCLK3 HIZ3_B TNEG3 TPOS3
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Table 11. Boundary Scan Register (Continued) BSR Bit
73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 Notes: 1)
Pin Name
TCLK3 LOS2 RNEG2 RPOS2 RCLK2 TNEG2 TPOS2 TCLK2 INT_B RDY WR_B RD_B ALE CS_B CS_B INTL CBLSEL CBLSEL TCLK5 TPOS5 TNEG5 RCLK5 RPOS5 RNEG5 LOS5 TCLK4 TPOS4 TNEG4 RCLK4 RPOS4 RNEG4 LOS4 TXOE CLKE
Cell Type
I O O O O Note 2 I I I O O Note 3 I I I I I I I I I I I O O O Note 2 O I I I O O O Note 2 O I I
Bit Symbol
TCLK3 LOS2 RNEG2 RPOS2 RCLK2 HIZ2_B TNEG2 TPOS2 TCLK2 INT_B RDYOUT RDYOEN WR_B RD_B ALE CS_B CS_B_TRI INTL CBLSEL_TRI CBLSEL_IN TCLK5 TPOS5 TNEG5 RCLK5 RPOS5 RNEG5 HIZ5_B LOS5 TCLK4 TPOS4 TNEG4 RCLK4 RPOS4 RNEG4 HIZ4_B LOS4 TXOE CLKE
2) 3)
LPOEN controls the LOOP[7:0] pins. Setting LPOEN to "1" configures LOOP[7:0] as outputs. The output value driven on the pins are determined by the values written to LPO[7:0]. Setting LPOEN to "0" High-Z all the pins. In this mode, the input values driven to these LOOP[7:0] can be read via LPI[7:0]. HIZ_B controls the RPOSx, RNEGx, and RCLKx pins. When HIZ_B is High, the outputs are enabled; when HIZ_B is Low, the outputs are placed in a high impedance state (High-Z). RDYOEN controls the ACK_B pin. Setting RDYOEN to "1" enables output on ACK_B. Setting ACKEN to "0" High Z the ACK_B pin.
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18. APPLICATIONS
+3.3V 0 .1 F
Note 1 RGND RV+ TV+ R TIP
0 .1 F
Note 1
+
+
68 F
Note 2
TGND
+3.3V
VCCIO
0 .1 F
R1 RECEIVE LINE R2
0 .1 F
GNDIO
+
R R IN G
T1 1:2 CS61884 One Channel
T R IN G TRANSMIT LINE T T IP
100 +3.3V 75 Cable
NC
T2 1:2 13.3k
CBLSEL REF
120 Cable
GND
Component R1 () R2 ()
T1/J1 100 Twisted Pair Cable 15 15
E1 75 Coaxial Cable 15 15
E1 120 Twisted Pair Cable 15 15
Notes:1) Required Capacitor between each TV+, RV+, VCCIO and TGND, RGND, GNDIO respectively. 2) Common decoupling capacitor for all TVCC and TGND pins.
Figure 17. Internal RX/TX Impedance Matching
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+3.3V 0 .1 F
Note 1 RGND RV+ TV+ R TIP
0 .1 F
Note 1
+
+
68 F
Note 2
TGND
1k 0 .1 F
R1
+3.3V
VCCIO
RECEIVE LINE
R2
0 .1 F
GNDIO
+
R R IN G
1k CS61884 One Channel
T R IN G T T IP
T1 1:2
TRANSMIT LINE
120 Cable
T2 1:2
CBLSEL
NC
100 75 Cable
13.3k
REF
GND
GND
Component R1 () R2 () Notes:
T1/J1 100 Twisted Pair Cable 12.5 12.5
E1 75 Coaxial Cable 9.31 9.31
E1 120 Twisted Pair Cable 15 15
1)Required Capacitor between each TV+, RV+, VCCIO and TGND, RGND, GNDIO respectively. 2)Common decoupling capacitor for all TVCC and TGND pins.
Figure 18. Internal TX, External RX Impedance Matching
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18.1 Transformer specifications
Recommended transformer specifications are shown in Table 12. Any transformer used with the CS61884 should meet or exceed these specifications.
Table 12. Transformer Specifications Descriptions Turns Ratio Receive/Transmit Primary Inductance Primary Leakage Inductance Secondary leakage Inductance Inter winding Capacitance ET-Constant Specifications 1:2 1.5mH min. @ 772 kHz 0.3 H max @ 772 kHz 0.4 H max @ 772 kHz 18pF max, primary to secondary 16V - s min.
mum symmetry of 40-60% and minimum stability of + 100ppm for both E1 and T1/J1 applications.
18.3 Designing for AT&T 62411
For information on requirements of the AT&T 62411 and the design of the appropriate system synchronizer, refer to Application Note AN012 "AT&T 62411 Design Considerations - Jitter and Synchronization" and Application Note AN011 "Jitter Testing Procedures for Compliance with AT&T 62411".
18.4 Line Protection
Secondary protection components can be added to the line interface circuitry to provide lightning surge and AC power-cross immunity. For additional information on the different electrical safety standards and specific applications circuit recommendations, refer to Application Note AN034 "Secondary Line Protection for T1 and E1 Cards".
18.2 Crystal Oscillator Specifications
When a reference clock signal is not available, a CMOS crystal oscillator may be used as the reference clock signal. The oscillator must have a mini-
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19. CHARACTERISTICS AND SPECIFICATIONS 19.1 Absolute Maximum Ratings
CAUTION: Operations at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Parameter DC Supply (referenced to RGND = TGND = 0V) DC Supply Input Voltage, Any Digital Pin except CBLSEL, MODE and LOOP(n) pins (referenced to GNDIO = 0V) Input Voltage CBLSEL, MODE & LOOP(n) Pins (referenced to GNDIO = 0V) Input voltage, RTIP and RRING Pins ESD voltage, Any pin Input current, Any Pin Maximum Power Dissipation, In package Ambient Operating Temperature Storage Temperature Note 1 Note 2 IIH Pp TA Tstg Symbol RV+ TV+ VCCIO VIH VIH Min. -0.5 GNDIO -0.5 GNDIO -0.5 TGND -0.5 2k -10 -40 -65 Max 4.0 4.0 4.6 5.3 VCCIO +0.5 TV+ +0.5 +10 1.73 85 150 Units V V V V V V V mA W C C
19.2 Recommended Operating Conditions
Parameter DC Supply DC Supply Ambient operating Temperature Power Consumption, T1/J1 Mode, 100 line load Power Consumption, E1 Mode, 75 line load Power Consumption, E1 Mode, 120 line load Notes 3, 4, 5 Notes 3, 4, 5 Notes 3, 4, 5 Symbol RV+, TV+ VCCIO TA
-
Min. 3.135 3.135 -40 -
Typ 3.3 3.3 25 970 810 750
Max 3.465 3.465 85 1900 1400 1300
Units V V C mW mW mW
Notes: 1. Human Body Model 2. Transient current of up to 100 mA will not cause SCR latch-up. Also TTIP, TRING, TV+ and TGND can withstand a continuous current of 100 mA. 3. Power consumption while driving line load over the full operating temperature and power supply voltage range. Includes all IC channels and loads. Digital inputs are within 10% of the supply rails and digital outputs are driving a 50pF capacitive load. 4. Typical consumption corresponds to 50% ones density for E1/T1/J1 modes and medium line length setting for T1/J1 mode at 3.3Volts. 5. Maximum consumption corresponds to 100% ones density for E1/T1/J1 modes and maximum line length settings for T1/J1 mode at 3.465Volts. 6. This specification guarantees TTL compatibility (VOH = 2.4 V @ IOUT = -400 A). 7. Output drivers are TTL compatible. 8. Pulse amplitude measured at the output of the transformer across a 75 load. 9. Pulse amplitude measured at the output of the transformer across a 120 load. 10. Pulse amplitude measured at the output of the transformer across a 100 load for all line length settings.
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19.3 Digital Characteristics
(TA = -40C to 85C; TV+, RV+ = 3.3 V 5%; GND = 0 V) Parameter High-Level Input Voltage Low-Level Input Voltage LOOP[7:0] Low-Level Input Voltage LOOP[7:0] Mid-Level Input Voltage LOOP[7:0] High-Level Input Voltage High-Level Output Voltage IOUT = -400 A Low-Level Output Voltage IOUT = 1.6 mA Input Leakage Current Input leakage for LOOP pins Notes 6, 7 Notes 6, 7 Note 6 Note 6 Symbol VIH VIL VIHL VIHM VIHH VOH VOL Min. 2.0 Typ Max 0.8 1/3 VCCIO-0.2 Units V V V V V V V A A
1/3 VCCIO +0.2 1/2 VCCIO 2/3 VCCIO-0.2 2/3 VCCIO +0.2 2.4 -10 -150 0.4 +10 +150
19.4 Transmitter Analog Characteristics
(TA = -40C to 85C; TV+, RV+ = 3.3 V 5%; GND = 0 V) Parameter Output Pulse Amplitudes Notes 8, 9, 10 E1 75 E1 120 T1/J1 100 Min. 2.14 2.7 2.4 0.95 0.95 0.95 -0.15 -0.3 -0.237 12.6 -29 - 14 - 14 - 14 - 14 - 14 - 14 Typ 2.37 3.0 3.0 - 20 - 19 - 18 - 19 - 19 - 18 0.010 0.009 0.007 0.015 Max 2.6 3.3 3.6 1.05 1.05 1.05 0.15 0.3 0.237 0.020 0.025 0.025 0.050 50 V V V dBm dBm dB Units V V V
Ratio of Positive to Negative pulses T1/J1 100 Notes 8, 9, 10 E1, amplitude at center of pulse interval E1, width at 50% of nominal amplitude Pulse Amplitude of a space T1/J1 100 E1 120 E1 75 (T1/J1 100 only)
Power in 2 kHz band about 772 kHz Notes 11, 12
Power in 2 kHz band about 1.544 MHz Notes 11, 12 (referenced to power in 2 kHz band at 772 kHz, T1/J1 100 only) Transmit Return Loss - E1 Notes 11, 12, 13 Transmit Return Loss - T1/J1 Notes 11, 12, 13 Jitter Added by the Transmitter Notes 11, 14 Transmitter Short Circuit Current per channel 51 kHz to 102 kHz 102 kH to 2048 kHz 2048 kHz to 3072 kHz 51 kHz to 102 kHz 102 kHz to 2048 kHz 2048 kHz to 3072 kHz 10 Hz - 8 kHz 8 kHz - 40 kHz 10 Hz - 40 kHz Broad Band
dB
UI
mA RMS
DS485PP4
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CS61884
19.5 Receiver Analog Characteristics
(TA = -40C to 85C; TV+, RV+ = 3.3 V 5%; GND = 0 V)) Parameter Allowable Cable Attenuation @ 1024kHz and 772kHz RTIP/RRING Input Impedance (Internal Line matching mode) Note 11 RTIP/RRING Input Impedance (External Line matching mode) Note 11 Receiver Dynamic Range Signal to Noise margin (Per G.703, O151 @ 6dB cable Atten). Note 11 Receiver Squelch Level LOS Threshold LOS Hysteresis Data Decision Threshold Note 11 Data Decision Threshold Note 11 Input Jitter Tolerance - E1 Notes 11, 15, 17 Input Jitter Tolerance - T1/J1 Notes 11, 15, 17 Input Return Loss - E1/T1/J1 Notes 11, 12, 13 E1 Modes T1/J1 Modes 1 Hz - 1.8 Hz 20 Hz - 2.4 kHz 18 kHz - 100 kHz 0.1 Hz - 1 Hz 4.9 Hz - 300 kHz 10kHz - 100 kHz 51 kHz - 102 kHz 102 kHz - 2048 kHz 2048 kHz - 3072 kHz T1/J1 100 Load E1 120 Load E1 75 Load T1/J1 100 Load E1 120 Load E1 75 Load Min. 0.5 41 56 18 1.5 0.2 138 28 0.4 - 18 - 18 - 18 Typ 140 14k 50 14K 14k 14K - 18 150 200 50 50 65 - 28 - 30 - 27 Max - 12 59 74 Units dB
Vp dB mV mV mV % of peak % of peak UI
UI
dB
Notes: 11. Parameters guaranteed by design and characterization. 12. Using components on the CDB61884 evaluation board in Internal Match Impedance Mode. 13. Return loss = 20log10 ABS((Z1 + Z0) / (Z1 - Z0)) where Z1 - impedance of the transmitter or receiver, and Z0 = cable impedance. 14. Assuming that jitter free clock is input to TCLK. 15. Jitter tolerance for 0 dB for T1/J1 input signal levels and 6 dB for E1 input signal levels. Jitter tolerance increases at lower frequencies. HDB3/B8ZS coders enabled. 16. In Data Recovery Mode. 17. Jitter Attenuator in the receive path.
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DS485PP4
CS61884
19.6 Jitter Attenuator Characteristics
(TA = -40C to 85C; TV+, RV+ = 3.3 V 5%; GND = 0 V) Parameter Jitter Attenuator Corner Frequency Note 11, 19 (Depends on JACF Bit in host mode) E1 Jitter Attenuation Note 11, 18 T1/J1 Jitter Attenuation Note 11, 18 Attenuator Input Jitter Tolerance before FIFO over flow and under flow Note 11 Delay through Jitter Attenuator Only Note 11 Intrinsic Jitter in Remote Loopback T1/J1 Modes T1/J1 Modes E1 Modes E1 Modes 3 Hz to 40 Hz 400 Hz to 100 kHz 1 Hz to 20 Hz 1 kHz 1.4KHz to 100KHz 32-bit FIFO 64-bit FIFO 32-bit FIFO 64-bit FIFO Notes 11, 17 Min. + 0.5 - 19.5 0 - 33.3 - 40 Typ 3.78 7.56 1.25 2.50 24 56 16 32 Max 0.11 Units Hz
dB dB
UI UI UI UI UI
Notes: 18. Attenuation measured with sinusoidal input filter equal to 3/4 of measured jitter tolerance. Circuit attenuates jitter at 20 dB/decade above the corner frequency. Output jitter can increase significantly when more than 28 UI's are input to the attenuator. 19. Measurement is not effected by the position of the Jitter Attenuator.
DS485PP4
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CS61884
+ 10
+ 0.5 0 -6 - 10 TYP. T1 @ 7.56Hz CF
ITU G.736
Attenuation in dB
- 19.5 - 20
- 30 AT&T 62411 Minimum Attenuation - 40 TYP. E1 @ 2.5 Hz CF - 50 TYP. T1 @ 3.78Hz CF
- 60
AT&T 62411 Maximum Attenuation TYP. E1 @ 1.25 Hz CF
- 70 1 2 10 20 40 57 100 400 1K 1.4K 10K 100K
Frequency in Hz
Figure 19. Jitter Transfer Characteristic vs. G.736, TBR 12/13 & AT&T 62411
1000
300 TYP. E1 Performance 138 100
PEAK TO PEAK JITTER (UI)
AT&T 62411 28 18 10
TYP. T1 Performance
1.5 1 .4 .2 .1 1 1.8 4.9 10 20
ITU G.823
100
300
1k
2.4k
10k 18k
100k
FREQUENCY IN Hz
Figure 20. Jitter Tolerance Characteristic vs. G.823 & AT&T 62411
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DS485PP4
CS61884
19.7 Master Clock Switching Characteristics
Parameter MASTER CLOCK (MCLK) Master Clock Frequency Master Clock Frequency Master Clock Tolerance Master Clock Duty Cycle E1 Modes T1/J1 Modes MCLK MCLK -100 40 50 2.048 1.544 +100 60 MHz MHz ppm % Symbol Min. Typ Max Units
19.8 Transmit Switching Characteristics
Parameter E1 TCLK Frequency E1 TPOS/TNEG Pulse Width (RZ Mode) T1/J1 TCLK Frequency TCLK Tolerance (NRZ Mode) TCLK Duty Cycle TCLK Pulse Width TCLK Burst Rate TCLK Falling to TPOS/TNEG Hold time (NRZ Mode) TXOE Asserted Low to TX Driver HIGH-Z TCLK Held Low to Driver HIGH-Z Note 21 Note 22 tsu2 th2 TPOS/TNEG to TCLK Falling Setup Time (NRZ Mode) tpwh2/tpw2 1/tpw2 Symbol 1/tpw2 Min. 236 -50 20 25 25 8 Typ 2.048 244 1.544 12 Max 252 50 90 20 1 20 Units MHz nS MHz PPM % nS MHz nS nS S S
19.9 Receive Switching Characteristics
* All parameters guaranteed by production, characterization or design.
Parameter RCLK Duty Cycle E1 RCLK Pulse Width E1 RPOS/RNEG Pulse Width (RZ Mode E1 RPOS/RNEG to RCLK rising setup time E1 RPOS/RNEG to RCLK hold time T1/J1 RCLK Pulse Width T1/J1 RPOS/RNEG Pulse Width (RZ Mode) T1/J1 POS/RNEG to RCLK rising setup time T1/J1 RPOS/RNEG to RCLK hold time RPOS/RNEG Output to RCLK Output (RZ Mode) Rise/Fall Time, RPOS, RNEG, RCLK, LOS outputs tr, tf tsu th tsu th Symbol Min. 40 196 200 150 200 259 250 150 200 Typ 50 244 244 244 244 324 324 324 324 Max 60 328 300 388 400 10 85 Units % nS nS nS nS nS nS nS nS nS nS
Notes: 20. Output load capacitance = 50pF. 21. MCLK is not active. 22. Parameters guaranteed by design and characterization.
DS485PP4
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CS61884
RCLK
tsu
RPOS/RNEG CLKE = 1 RPOS/RNEG CLKE = 0
th
tsu
th
Figure 21. Recovered Clock and Data Switching Characteristics
tpw2 tpwh2 TCLK tsu2 th2
TPOS/TNEG
Figure 22. Transmit Clock and Data Switching Characteristics
tr 90% Any Digital Output 10%
Figure 23. Signal Rise and Fall Characteristics
tf 90% 10%
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DS485PP4
CS61884
19.10 Switching Characteristics - Serial Port
Parameter SDI to SCLK Setup Time SCLK to SDI Hold Time SCLK Low Time SCLK High Time SCLK Rise and Fall Time CS to SCLK Setup Time SCLK to CS Hold Time CS Inactive Time SDO Valid to SCLK CS to SDO High Z Note 23 Note 23 Symbol tdc tcdh tcl tch tr, tf tcc tcch tcwh tcdv tcdz Min. Typ. 20 20 50 50 15 20 20 70 60 50 Max Unit ns ns ns ns ns ns ns ns ns ns
Notes: 23. If SPOL = 0, then CS should return high no sooner than 20 ns after the 16th rising edge of SCLK during a serial port read.
CS SCLK SDI SDO CLKE=0 SDO CLKE=1 LAST ADDR BIT
tcdv
D0 D1 D6 D7
tcdz
tcdv
D0 D1 D6 D7 HIGH Z
Figure 24. Serial Port Read Timing Diagram
tcwh
CS
tcc
SCLK
tch
tcl
tcch
tdc
SDI LSB
tcdh
LSB
tcdh
MSB
Figure 25. Serial Port Write Timing Diagram
DS485PP4
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CS61884
19.11 Switching Characteristics - Parallel Port (Multiplexed Mode)
* All paramters guaranteed by production, characterization or design.
Parameter Pulse Width AS or ALE High Muxed Address Setup Time to AS or ALE Low Muxed Address Hold Time Delay Time AS or ALE to WR, RD or DS CS & R/W Setup Time Before WR, RD or DS Low CS & R/W Hold Time Pulse Width, WR, RD, or DS Write Data Setup Time Write Data Hold Time Output Data Delay Time from RD or DS Low Read Data Hold Time Delay Time WR, RD, or DS to ALE or AS Rise WR or RD Low to RDY Low WR or RD Low to RDY High WR or RD High to RDY HIGH-Z DS Low to ACK High DS Low to ACK Low DS High to ACK HIGH-Z Ref. # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Min. 25 10 5 5 0 0 70 30 30 5 30 Typ. Max 100 55 100 40 65 100 40 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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DS485PP4
CS61884
1
ALE 12 4 7
WR 5 CS 2 3 6
8
9 Write Data
D[7:0]
ADDRESS
15 HIGH-Z RDY 13 14 HIGH-Z
Figure 26. Parallel Port Timing - Write; Intel Multiplexed Address / Data Bus Mode
1
ALE 12 4 7
RD 5 CS 6
2 D[7:0]
3
10
11
ADDRESS
Read Data
15 14
HIGH-Z RDY 13
HIGH-Z
Figure 27. Parallel Mode Port Timing - Read; Intel Multiplexed Address / Data Bus Mode
DS485PP4
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CS61884
1
AS 12 DS 4 7
R/W 5 CS 6
2
3
8
9
D[7:0]
ADDRESS 17 HIGH-Z
Write Data 18 HIGH-Z 16
ACK
Figure 28. Parallel Port Timing - Write in Motorola Multiplexed Address / Data Bus
1
AS 12 DS 4 7
R/W 5 CS 6
2
3
10
11
D[7:0]
ADDRESS 17 HIGH-Z
Read Data 18 HIGH-Z 16
ACK
Figure 29. Parallel Port Timing - Read in Motorola Multiplexed Address / Data Bus
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DS485PP4
CS61884
19.12 Switching Characteristics- Parallel Port (Non-multiplexed Mode)
* All paramters guaranteed by production, characterization or design.
Parameter Address Setup Time to WR, RD or DS Low Address Hold Time CS & R/W Setup Time Before WR, RD or DS Low CS & R/W Hold Time Pulse Width, WR, RD, or DS Write Data Setup Time Write Data Hold Time Output Data Delay Time from RD or DS Read Data Hold Time WR or RD Low to RDY Low WR, RD or DS Low to RDY High WR, RD or DS High to RDY HIGH-Z DS Low to ACK High DS Low to ACK Low DS High to ACK HIGH-Z Ref. # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Min. 10 5 0 0 70 30 30 5 Typ. Max 100 55 100 40 65 100 40 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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CS61884
1
2
A[4:0]
ADDRESS
ALE
(pulled high) 5
WR 3 4
CS 6 7
D[7:0]
Write Data
11 HIGH-Z RDY 10
12 HIGH-Z
Figure 30. Parallel Port Timing - Write in Intel Non-Multiplexed Address / Data Bus Mode
1
2
A[4:0]
ADDRESS
ALE
(pulled high) 5
RD 3 CS 8 9 4
D[7:0]
Read Data
11 HIGH-Z RDY 10
12 HIGH-Z
Figure 31. Parallel Port Timing - Read in Intel Non-Multiplexed Address / Data Bus Mode
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DS485PP4
CS61884
1
2
A[4:0]
ADDRESS
AS
(pulled high) 5
DS
R/W 3 CS 6 7 4
D[7:0]
Write Data
14 HIGH-Z ACK 13
15 HIGH-Z
Figure 32. Parallel Port Timing - Write in Motorola Non-Multiplexed Address / Data Bus Mode
1
2
A[4:0]
ADDRESS
AS
(pulled high) 5
DS
R/W 3 CS 8 9 4
D[7:0]
Read Data
14 HIGH-Z ACK 13 15 HIGH-Z
Figure 33. Parallel Port Timing - Read in Motorola Non-Multiplexed Address / Data Bus Mode
DS485PP4
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CS61884
19.13 Switching Characteristics - JTAG
Parameter Cycle Time TMS/TDI to TCK Rising Setup Time TCK Rising to TMS/TDI Hold Time TCK Falling to TDO Valid Symbol tcyc tsu th tdv Min. 200 50 50 Max 70 Units nS nS nS nS
tcyc
TCK tsu TMS TDI TDO tdv th
Figure 34. JTAG Switching Characteristics
68
DS485PP4
CS61884
20. COMPLIANT RECOMMENDATIONS AND SPECIFICATIONS
AT&T Pub 62411 FCC Part 68 ANSI T1.102 ANSI T1.105 ANSI T1.231 ANSI T1.403 ANSI T1.408 Bell Core TR-TSY-000009 Bell Core GR-253-Core Sonet Bell Core GR-499-Core ETSI ETS 300-011 ETSI ETS 300-166 ETSI ETS 300-233 IEEE 1149.1 ETSI TBR 12/13 ITU-T I.431 ITU-T G.703 ITU-T G.704 ITU-T G.706 ITU-T G.732 ITU-T G.735 ITU-T G.736 ITU-T G.742 ITU-T G.772 ITU-T G.775 ITU-T G.783 ITU-T G.823 ITU-T O.151 OFTEL OTR-001
DS485PP4
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CS61884
21. FBGA PACKAGE DIMENSIONS
70
DS485PP4
CS61884
22. LQFP PACKAGE DIMENSIONS
144L LQFP PACKAGE DRAWING
E E1
D D1
1 e A1 L B A
MIN --0.002 0.007 0.854 0.783 0.854 0.783 0.016 0.000 L 0.018 * Nominal pin pitch is 0.50 mm Controlling dimension is mm. JEDEC Designation: MS022 DS485PP4
DIM A A1 B D D1 E E1 e*
INCHES NOM 0.55 0.004 0.008 0.866 BSC 0.787 BSC 0.866 BSC 0.787 BSC 0.020 4 0.024
MAX 0.063 0.006 0.011 0.878 0.791 0.878 0.791 0.024 7.000 0.030
MIN --0.05 0.17 21.70 19.90 21.70 19.90 0.40 0.00 0.45
MILLIMETERS NOM 1.40 0.10 0.20 22.0 BSC 20.0 BSC 22.0 BSC 20.0 BSC 0.50 BSC 4 0.60
MAX 1.60 0.15 0.27 22.30 20.10 22.30 20.10 0.60 7.00 0.75
71

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